MAX14821 datasheet(14/29 Pages) MAXIM

14 / 29 page

�� Maxim Integrated Products 14

MAX14821

IO-Link Device Transceiver

Pin/Bump Configurations

Pin/Bump Descriptions

NAME

FUNCTION

TQFN-EP

WLP

LDOIN

5V Linear Regulator Input. Bypass LDOIN to GND with a 0.1FF ceramic capacitor.

5V Power-Supply Input and 5V Linear Regulator Output. Bypass V5 to GND with a 0.1FF

ceramic capacitor for 10mA load capability. Add the recommended compensation network

to increase the source capability to 30mA. See the 5V and 3.3V Linear Regulators section for

more information.

LDO33

3.3V Linear Regulator Output. Bypass LDO33 to GND with a 1FF ceramic capacitor.

IRQ

Active-Low Interrupt Request Output. IRQ is a push-pull output referenced to VL.

SCLK

SPI Clock Input

Active-Low SPI Chip-Select Input

SDO

SPI Serial-Data Output

SDI

SPI Serial-Data Input

Logic-Level Supply Input. VL defines the logic levels on all the logic inputs and outputs.

Bypass VL to GND with a 0.1FF ceramic capacitor.

I.C.

Internally Connected. Connect to VL or leave unconnected.

VCC

I.C.

SDI

SDO

*EP

*CONNECT EXPOSED PAD TO GND.

C/Q

11 TXQ

GND

12 TXC

TQFN

TOP VIEW

MAX14821

TOP VIEW

(BUMP SIDE DOWN)

WLP

1234

VCC

LDOIN

LDO33

SCLK

C/Q

IRQ

SDO

GND

I.C.

SDI

TXC

TXQ

TXEN

MAX14821 Datasheet(PDF) 14 Page - Maxim Integrated Products

MAX14821 Datasheet(HTML) 14 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL