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ADS6142-HT Datasheet(PDF) 7 Page - Texas Instruments

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Part # ADS6142-HT
Description  14-BITS, 65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
PDF  49 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS6142-HT Datasheet(HTML) 7 Page - Texas Instruments

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ADS6142-HT
www.ti.com
SLWS234
– DECEMBER 2011
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
TJ = -40°C to 125°C
TJ = 210°C
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
SUPPLIES
AVDD
Analog supply voltage
3
3.3
3.6
3
3.3
3.6
V
CMOS Interface
1.65
1.8 to 3.3
3.6
1.65
1.8 to 3.3
3.6
V
Output buffer supply
DRVDD
voltage
LVDS Interface
3
3.3
3.6
3
3.3
3.6
V
ANALOG INPUTS
Differential input voltage range
2
2
Vpp
VIC
Input common-mode voltage
1.5
± 0.1
1.5
± 0.1
V
Voltage applied on VCM in external reference mode
1.45
1.5
1.55
1.45
1.5
1.55
V
CLOCK INPUT
Input clock sample rate, FS
1
65
1
65 MSPS
Sine wave, ac-coupled
0.4
1.5
0.4
1.5
Input clock amplitude
LVPECL, ac-coupled
± 0.8
± 0.8
differential
Vpp
LVDS, ac-coupled
± 0.35
± 0.35
(VCLKP – VCLKM)
LVCMOS, ac-coupled
3.3
3.3
Input Clock duty cycle
35%
50%
65%
35%
50%
65%
DIGITAL OUTPUTS
For CLOAD ≤ 5 pF and
DEFAULT
DEFAULT
DRVDD
≥ 2.2 V
strength
strength
Output buffer drive
For CLOAD > 5 pF and
MAXIMUM
MAXIMUM
strength (1)
DRVDD
≥ 2.2 V
strength
strength
MAXIMUM
MAXIMUM
For DRVDD
< 2.2 V
strength
strength
CMOS Interface, maximum
10
10
buffer strength
Maximum external load
LVDS Interface, without
5
5
CLOAD
capacitance from each
pF
internal termination
output pin to DRGND
LVDS Interface, with
10
10
internal termination
RLOAD
Differential load resistance (external) between the
100
100
Ω
LVDS output pairs
TJ
Operating junction temperature range
-40
125
210
°C
(1)
See Output Buffer Strength Programmability in the application section.
Copyright
© 2011, Texas Instruments Incorporated
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