ADS6142-HT datasheet(15/49 Pages) TI1

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(3/8) AVDD

ToParallelPin

(SCLK,SDATA,SEN)

AVDD

GND

(5/8) AVDD

GND

ADS6142-HT

www.ti.com

SLWS234

– DECEMBER 2011

DEVICE PROGRAMMING MODES

The ADS6142 has several features that can be easily configured using either parallel interface control or serial

interface programming.

USING SERIAL INTERFACE PROGRAMMING ONLY

To program using the serial interface, the internal registers must first be reset to their default values, and the

RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are

used to access the internal registers of the ADC. The registers are reset either by applying a pulse on the

RESET pin or by a high setting on the

<RST> bit (D4 in register 0x00). The Serial Interface section describes

USING PARALLEL INTERFACE CONTROL ONLY

To control the device using the parallel interface, keep RESET tied high (AVDD). Now SEN, SCLK, SDATA, and

PDN function as parallel interface control pins. These pins can be used to directly control certain modes of the

ADC by connecting them to the correct voltage levels (as described in Table 3 to Table 5). There is no need to

apply a reset pulse.

Frequently used functions are controlled in this mode

— standby, selection between LVDS/CMOS output format,

internal/external reference, and 2s complement/straight binary output format.

Figure 5. Simple Scheme to Configure Parallel Pins

DESCRIPTION OF PARALLEL PINS

Table 3. SCLK (Analog Control Pin)

SCLK

DESCRIPTION

Internal reference and 0 dB gain (full-scale = 2 VPP)

(3/8) AVDD

External reference and 0 dB gain (full-scale = 2 VPP)

(5/8) AVDD

External reference and 3.5 dB coarse gain (full-scale = 1.34 VPP)

AVDD

Internal reference and 3.5 dB coarse gain (full-scale = 1.34 VPP)

Table 4. SEN (Analog Control Pin)

SEN

DESCRIPTION

2s Complement format and DDR LVDS interface

(3/8) AVDD

Straight binary format and DDR LVDS interface

(5/8) AVDD

Straight binary and parallel CMOS interface

AVDD

2s Complement format and parallel CMOS interface

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