TLC320AD55CDW datasheet(17/41 Pages) TI1

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2–5

2.2.5

Hardware Program Terminal (FC)

This input provides for hardware programming requests for secondary communication. It works in

conjunction with the control bit D00 of the secondary data word. The signal on FC is latched 1/2 shift clock

after the rising edge of the next internally generated primary frame-sync interval. FC should be tied low when

not being used (see Section 3.2 Secondary Serial Communication).

2.2.6

Frame-Sync

The frame-sync signal indicates that the device is ready to send and receive data. The data transfer from

DOUT and into DIN begins on the falling edge of the frame-sync signal.

The frame sync is generated internally and goes low on the rising edge of SCLK and remains low during

the 16-bit data transfer.

2.2.7

Multiplexed Analog Input

The two differential analog inputs (INP and INM or AUXP and AUXM) are multiplexed into the sigma-delta

modulator. The performance of the AUX channel is similar to the normal input channel.

2.2.8

Analog Input

The signal applied to the terminals INM and INP should be differential to preserve the device specifications

(see Figure 2–3). A single-ended input signal should always be converted to a differential input signal prior

to being used by the TLC320AD55C. The signal source driving the analog inputs (INM, INP, AUXM, AUXP)

should have a low source-impedance for lowest noise performance and accuracy.

4 V

2.5 V

1 V

4 V

2.5 V

1 V

INP

INM

TLC320AD55C

Figure 2– 3. Differential Analog Input Configuration

TLC320AD55CDW Datasheet(PDF) 17 Page - Texas Instruments