TLC320AD55CDW datasheet(10/41 Pages) TI1

10 / 41 page

1–4

1.5

Terminal Functions

TERMINALS

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AUXM

Inverting input to auxiliary analog input

AUXP

Noninverting input to auxiliary analog input

ALT DATA

Signals on ALT DATA are routed to DOUT during secondary communiction when phone

mode is enabled.

DIN

Data input. DIN receives the DAC input data and command information from the DSP

and is synchronized to SCLK.

DOUT

Data output. DOUT transmits the ADC output bits and is synchronized to SCLK. DOUT

is at Hi-Z when FS is not activated.

DVDD

Digital power supply

DVSS

Digital ground

Function control. FC is sampled and latched on the rising edge of FS for the primary serial

communication. Refer to Section 3 Serial Communications for more details.

FLAG 0

During phone mode, FLAG 0 contains the value set in control 2 register.

FLAG 1

During phone mode, FLAG 1 contains the value set in control 2 register.

Frame sync. When FS goes low, the serial communication port is activated. In all serial

transmission modes, FS is held low during bit transmission. Refer to Section 3 Serial

Communications for a detailed description.

INM

Inverting input to analog input

INP

Noninverting input to analog input

MCLK

Master clock. MCLK derives the internal clocks of the sigma-delta analog interface

circuit.

OUTM

Inverting output of the DAC analog power amplifier. Functionally identical with and

complementary to OUTP. OUTM and OUTP can drive 600

Ω differentially. OUTM should

not be used alone for single-ended operation.

OUTP

Noninverting output of the DAC analog power amplifier. OUTM and OUTP can drive

600

Ω differentially. OUTP should not be used alone for single-ended operation.

PWRDWN

Power down. When PWRDWN is pulled low, the device goes into a power-down mode;

the serial interface is disabled and most of the high-speed clocks are disabled. However,

all of the registers’ values are sustained and the device resumes full power operation

without reinitialization when PWRDWN is pulled high again. PWRDWN resets the

counters only and preserves the programmed register contents. Refer to Section 2.2.1.3

Software and Hardware Power-Down.

REFCAPADC

Analog-reference voltage connection for external capacitor for the ADC. The nominal

voltage on REFCAPADC is 3.4 V. A buffer must be used when this voltage is used

externally. REFCAPADC is not to be used as the mid-supply voltage reference for

single-ended operation.

REFCAPDAC

Analog-reference voltage connection for external capacitor for the DAC. The nominal

voltage on REFCAPDAC is 3.4 V. A buffer must be used when this voltage is used

externally.

RESET

Reset. The reset function initializes all of the internal registers to their default values. The

serial port can be configured to the default state accordingly. Refer to Appendix A Table

A–2 Control 1 Register and Section 2.2.1 Reset and Power-Down for more detailed

descriptions.

SCLK

Shift clock. SCLK is derived from MCLK and clocks serial data into DIN and out of DOUT.

NOTE 1: All digital inputs and outputs are TTL compatible unless otherwise noted.

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