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TLC320AD55CDW Datasheet(PDF) 31 Page - Texas Instruments |
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TLC320AD55CDW Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 41 page ![]() 4–5 4.4.8 Power Supplies, VDD(ADC) = VDD(DAC) = DVDD = 5 V, No Load (unless otherewise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDD (ADC) Power supply current ADC Operating 12 20 mA IDD (ADC) Power supply current, ADC Power-down 400 µA IDD (DAC) Power supply current DAC Operating 16 24 mA IDD (DAC) Power supply current, DAC Power-down 2.5 mA IDD (Digital) Power supply current digital Operating 2 6 mA IDD (Digital) Power supply current, digital Power-down 300 µA PD Power dissipation Operating 150 250 mW PD Power dissi ation Power-down 16 30 mW 4.4.9 Timing Requirements (see Notes 9 and 10) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td1 Delay time, SCLK ↑ to FS↓ 10 15 td2 Delay time, SCLK ↑ to DOUT 6 20 tsu Setup time, DIN before SCLK ↓ 20 th Hold time, DIN after SCLK ↓ CL = 20 pF 20 ns ten Enable time, FS ↓ to DOUT 10 25 tdis Disable time, FS ↑ to DOUT Hi-Z 20 td3 Delay time MCLK ↓ to SCLK↑ 25 50 NOTES: 9. Refer to Figure 3–1 for timing diagram. 10. When FS occurs after SCLK, it shortens the MSB (D15) duration. |
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