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TLC320AD55CDW Datasheet(PDF) 23 Page - Texas Instruments |
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TLC320AD55CDW Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 41 page ![]() 3–5 In Figure 3–6, FC hardware terminal 15 is left in its nonasserted state (0). FC is asserted through software by embedding an asserted high level (1) in the LSB of the 16-bit primary word. This is possible when not in 16-bit mode (control 1 register bit 2 = 0) because the user is using only 15 bits of DAC information. ADC Data Out ADC Data Out DAC Data In DOUT DOUT DAC Data In DIN ADC Data Out All Bits 0 16 SCLKs 16 SCLKs 16 SCLKs FS FC Communication Frame 1 (CF1) NOTE A: For a read cycle, the last 8 bits are don’t care. D15–D1 D0 = 0 D15–D1 D0 = 1 0 (Secondary Read) (Secondary Read or Write) (Secondary Write) Primary Secondary Primary No Secondary Request 64 FCLKs† 64 FCLKs† 32 FCLKs† Register Data Secondary Update † See Fk divide register in Appendix A. Communication Frame 2 (CF2) ADC Data Out 8 SCLKs Software FC Bit Figure 3– 6. Software FC Secondary Request (Phone Mode Disabled) Table 3–2 shows the secondary communications format. D13 is the R/W bit, the read/not-write bit. D12 through D8 are address bits. The register map is specified in the register set section in Appendix A. D7 through D0 are data bits. The data bits are values for the specified register addressed by data bits D12 through D8. Table 3– 2. Secondary Communication Data Format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X R/W A A A A A D D D D D D D D 3.3 Conversion Rate Versus Serial Port The SCLK frequency can be programmed independently from the FCLK frequency. This can create a problem with the interpretation of the serial port data. The serial port is designed to initiate a primary communication every 64 SCLKs. There must be an integer number of SCLKs ≥ 40 per sample period. Two examples follow to demonstrate the possible output of the serial port. SCLK must be fast enough to collect all data from each frame. Example 1: MCLK = 4.096 MHz, sample rate = 8 kHz, 8 kHz = MCLK/ (Fk × 256), set Fk = 2, SCLK = MCLK/ (Fsclk × 2), set Fsclk = 2, SCLK = 1.024 MHz. With this configuration, SCLK = sample rate × 128. Therefore, each primary communication is a valid sample. |
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