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TLC320AD55CDW Datasheet(PDF) 36 Page - Texas Instruments

Part # TLC320AD55CDW
Description  Sigma-Delta Analog Interface Circuit
PDF  41 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLC320AD55CDW Datasheet(HTML) 36 Page - Texas Instruments

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A–2
Table A– 3. Control 2 Register
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
X
X
–
–
–
–
–
–
Reserved
–
–
X
–
–
–
–
–
Decimator FIR overflow flag (valid only during read cycle)
–
–
–
X
–
–
–
–
FLAG 1 output value
–
–
–
–
X
–
–
–
FLAG 0 output value
–
–
–
–
–
1
–
–
Phone mode enabled
–
–
–
–
–
0
–
–
Phone mode disabled
–
–
–
–
–
–
0
–
Normal operation with decimator FIR filter
–
–
–
–
–
–
1
–
Bypass decimator FIR filter
–
–
–
–
–
–
–
0
Normal operation with interpolator filter
–
–
–
–
–
–
–
1
Bypass interpolator FIR filter
Default register value: 00000000
Writing zeros to the reserved bits is suggested.
Table A– 4. Fk Divide Register
D7
D6
D5
D4
D3
D2
D1
D0
DIVIDE VALUE
1
1
1
1
1
1
1
1
255
1
000
0000
128
0
010
0000
32
0
000
0001
1
0
0
0
0
0
0
0
0
256
Default register value: 00001000
The oversampling clock (FCLK) is set as MCLK/(Fk
× 4). MCLK/(Fk × 256) is the sample frequency
(conversion rate) for the converter. When Fk is programmed to zero, its value is interpreted as 256.



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