TLC320AD55CDW datasheet(14/41 Pages) TI1

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2–2

DOUT is released from the high-impedance state on the falling edge of the primary or secondary frame-sync

interval. In addition, each register can be read back during DOUT secondary communications by setting the

read bit D13 to 1 in the addressed register (refer to Appendix A). When the register is in the read mode, no

data can be written to the register during this cycle. To return this register to the write mode requires a

subsequent secondary communication.

2.1.6

Sigma-Delta ADC

The sigma-delta ADC is a fourth-order, sigma-delta modulator with 64-times oversampling. The ADC

provides high-resolution, low-noise performance using oversampling techniques.

2.1.7

Decimation Filter

The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating

with a ratio of 1:64. The output of this filter is a sixteen-bit, 2s-complement data word clocking at the sample

rate.

NOTE

The sample rate is determined through a programmable relationship of

MCLK/(Fk

× 256), Fk = 1,2,3,...,256

2.1.8

Sigma-Delta DAC

The sigma-delta DAC is a fourth-order, sigma-delta modulator with 64-times oversampling. The DAC

provides high-resolution, low-noise performance from a one-bit converter using oversampling techniques.

2.1.9

Interpolation Filter

The interpolation filter resamples the digital data at a rate of 64 times the incoming sample rate. The

high-speed data output from this filter is then used in the sigma-delta DAC.

2.1.10

Switched-Capacitor Filter (SCF)

A switched-capacitor filter network is implemented on the analog output to provide low-pass operation with

high rejection in the stop band.

2.1.11

Analog/Digital Loopback

The loopbacks provide a means of testing the ADC/DAC channels and can be used for in-circuit,

system-level tests. The loopbacks feed the appropriate output to the corresponding input on the device.

The test capabilities include an analog loopback between the two analog paths and a digital loopback

between the two digital paths. Each loopback is enabled by setting the D1 or D2 bit in control 1 register (see

Appendix A).

2.1.12

DAC Voltage Reference Enable

The DAC voltage reference can be disabled through the control 3 register. This allows the use of an external

voltage reference applied to the DAC channel modulator. By supplying an external reference, the user can

scale the output voltage range of this channel. The internal reference value is 3.6 V which provides a 6-V,

peak-to-peak, differential output. The ratio of an external reference to the internal reference determines the

output voltage range of the DAC channel as shown in the following equation:

O(PP) +

V(EXT REF)

3.6

NOTE

The distortion and noise specifications listed in Section 4 Specifications apply only

under the following condition:

V(EXT REF)

3.6

v 1

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