3–6

Example 2: All variables above remain the same except Fsclk = 1, SCLK = 2.048 MHz = sample

rate

× 256. In this configuration, two consecutive primary communications represent the

same data sample.

3.4

FIR Bypass Mode

An option is provided to bypass the FIR sections of the decimation filter and the interpolation filter. This is

selected through the control 2 register. The sinc filters of the two paths cannot be bypassed.

The timing requirements for this mode of operation are shown in Figure 3 –7.

ADC Data

Out

DOUT

Primary

Secondary

Primary

Secondary

Primary

18 – 4

DIN

3–0

See Note A

16 FCLKS

FS

ADC Data

Out

ADC Data

Out

NOTE A: The number of clocks between primary cycles is a function of FCLK. When either FIR is bypassed, this period

is 16 FCLKs. See Fk divide register in Appendix A.

Figure 3– 7. FIR Bypass Timing