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TLC320AD55CDW Datasheet(PDF) 37 Page - Texas Instruments |
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TLC320AD55CDW Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 41 page ![]() A–3 Table A– 5. Fsclk Divide Register D7 D6 D5 D4 D3 D2 D1 D0 DIVIDE VALUE 1 1 1 1 1 1 1 1 255 1 000 0000 128 0 010 0000 32 0 000 0001 1 0 0 0 0 0 0 0 0 256 Default register value: 00001000 SCLK is set by MCLK/(2 × Fsclk). SCLK is for the serial transfer of data to and from the TLC320AD55C. When Fsclk is programmed to zero, its value is interpreted as 256. Table A– 6. Control 3 Register D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION 0 0 0 0 1 0 0 0 DAC reference disabled 0 0 0 0 0 0 0 0 DAC reference enabled |
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