WM8351 datasheet(55/330 Pages) WOLFSON

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Production Data

WM8351

PD, April 2012, Rev 4.5

12.3.5

OPCLK CONTROL

When the GPIO5 pin is configured as CODEC_OPCLK, a clock derived from SYSCLK may be output

on this pin to provide clocking for other parts of the system. The frequency of this signal is derived

from SYSCLK and determined by OPCLK_DIV, as described in Table 14.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R40 (28h)

Clock Control

2:0

OPCLK_DIV

[2:0]

000

OPCLK Frequency (GPIO function)

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 5.5

101 = SYSCLK / 6

110 = Reserved

111 = Reserved

Table 14 OPCLK Control

12.3.6

SLOWCLK CONTROL

A slow clock derived from SYSCLK may be generated for de-bouncing of the Headphone Jack Detect

function or to set the timeout period for volume updates when zero-cross functions are used. This

clock is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE, as described in Table 15.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R11 (0Bh)

Power Mgmt

TOCLK_ENA

Slow clock enable. Used for both the

jack insert detect debounce circuit and

the zero cross timeout.

0 = slow clock disabled

1 = slow clock enabled

R40 (28h)

Clock Control

TOCLK_RATE

Slow Clock Selection (Used for volume

update timeouts and for jack detect

debounce)

0 = SYSCLK / 2

21 (Slower Response)

1 = SYSCLK / 2

19 (Faster Response)

Note: TOCLK_ENA can be accessed through R11 or through R40. Reading from or writing to either

Table 15 SLOWCLK Control

12.4 FLL

The integrated FLL can be used to generate SYSCLK from a wide variety of different reference

sources and frequencies. The FLL can accept a wide range of reference frequencies, which may be

high frequency (eg. 12.288MHz) or low frequency (eg. 32.768kHz). The FLL is tolerant of jitter and

may be used to generate a stable SYSCLK from a less stable input signal.

The FLL can take as input the external MCLK, or ADCLRCLK / DACLRCLK (in Slave modes), or the

32kHz crystal oscillator (or external 32kHz source). The FLL input reference source is selected using

the FLL_CLK_SRC, as described in Table 17. Choosing the 32kHz source as an input selects either

the 32kHz GPIO input or the internal 32kHz oscillator, as illustrated in Figure 33. For best audio

performance, it is recommended that a high frequency input clock (above 1MHz) is used.

The analogue and digital portions of the FLL may be enabled independently via FLL_OSC_ENA and

FLL_ENA. When initialising the FLL, the analogue circuit must be enabled first by setting

FLL_OSC_ENA. The digital circuit may then be enabled on the next register write or later. When

changing FLL settings, it is recommended that the digital circuit be disabled via FLL_ENA and then

re-enabled after the other register settings have been updated. When changing the input reference

frequency FREF, it is recommended that the FLL be reset by setting FLL_ENA to 0.

WM8351 Datasheet(PDF) 55 Page - Wolfson Microelectronics plc

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