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WM8351 Datasheet(PDF) 94 Page - Wolfson Microelectronics plc |
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WM8351 Datasheet(HTML) 94 Page - Wolfson Microelectronics plc |
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94 / 330 page  WM8351 Production Data w PD, April 2012, Rev 4.5 94 Right Justified Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the end of SLOT1 to the end of SLOT0 is determined by the selected word length of the interface of the WM8351. Figure 56 Right Justified Mode with TDM I2S Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 to the start of SLOT1 is determined by the selected word length of the interface of the WM8351. Figure 57 I2S Mode with TDM DSP/PCM Mode A, Master Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 (left) to the start of SLOT1 (left) is determined by the selected word length of the interface of the WM8351. Figure 58 DSP/PCM Mode A, Master Mode with TDM |
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