AD73460

–9–

REV. 0

PIN FUNCTION DESCRIPTIONS

Mnemonic

Function

WR

(Output) Memory Write Enable Output

IRQ2/

(Input) Edge- or Level-Sensitive Interrupt

PF7

(Input/Output) Request.

IRQL0/

(Input) Level-Sensitive Interrupt Requests

2

PF6

(Input/Output) Programmable I/O Pin

IRQL1/

(Input) Level-Sensitive Interrupt Requests

2

PF5

(Input/Output) Programmable I/O Pin

IRQE/

(Input) Edge-Sensitive Interrupt Requests

2

PF4

(Input/Output) Programmable I/O Pin

Mode D/

(Input) Mode Select Input—Checked Only During RESET

PF3

(Input/Output) Programmable I/O Pin During Normal Operation

Mode C/

(Input) Mode Select Input—Checked Only During RESET

PF2

(Input/Output) Programmable I/O Pin During Normal Operation

Mode B/

(Input) Mode Select Input—Checked Only During RESET

PF1

(Input/Output) Programmable I/O Pin During Normal Operation

Mode A/

(Input) Mode Select Input—Checked Only During RESET

PF0

(Input/Output) Programmable I/O Pin During Normal Operation

CLKIN,

(Inputs) Clock or Quartz Crystal Input

XTAL

CLKOUT

(Output) Processor Clock Output

SPORT0

(Inputs/Outputs) Serial Port I/O Pins

SPORT1

(Inputs/Outputs) Serial Port I/O Pins

IRQ1:0

(Inputs) Edge- or Level-Sensitive Interrupts,

FI

(Input) Flag In

3

FO

(Output) Flag Out

3

PWD

(Input) Power-Down Control Input

PWDACK

(Output) Power-Down Control Output

FL0, FL1,

(Outputs) Output Flags

FL2

A13 to A0

(Output) Address Output Pins for Program, Data, Byte, and I/O Space

D23 to D0

(Input/Output) Data I/O Pins for Program, Data, Byte, and I/O Space

VDD and

Power and Ground

GND

EZ-ICE Port

(Inputs/Outputs) For Emulation Use

ERESET

EMS

EE

ECLK

ELOUT

ELIN

EINT

EBR

EBG

NOTES

vector address when the pin is asserted, either by external devices, or set as a programmable flag.