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AD73460 Datasheet(PDF) 11 Page - Analog Devices |
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AD73460 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 32 page  AD73460 –11– REV. 0 VINN1 VINP1 ANALOG - MODULATOR SDI SDIFS SCLK2 REFCAP REFOUT SE ARESET SDOFS SDO AMCLK VINN2 VINP2 VINN3 VINP3 VINN4 VINP4 VINN5 VINP5 VINN6 VINP6 AFE SECTION SIGNAL CONDITIONING 0/38dB PGA DECIMATOR SERIAL I/O PORT SIGNAL CONDITIONING 0/38dB PGA DECIMATOR SIGNAL CONDITIONING 0/38dB PGA DECIMATOR SIGNAL CONDITIONING 0/38dB PGA DECIMATOR SIGNAL CONDITIONING 0/38dB PGA DECIMATOR SIGNAL CONDITIONING 0/38dB PGA DECIMATOR REFERENCE ANALOG - MODULATOR ANALOG - MODULATOR ANALOG - MODULATOR ANALOG - MODULATOR ANALOG - MODULATOR AD73460 Figure 2. Functional Block Diagram of Analog Front End Table II. PGA Settings for the Encoder Channel IxGS2 IxGS1 IxGS0 Gain (dB) 000 0 001 6 010 12 011 18 100 20 101 26 110 32 111 38 ADC Each channel has its own ADC consisting of an analog sigma- delta modulator and a digital antialiasing decimation filter. The sigma-delta modulator noise-shapes the signal and produces 1-bit samples at a DMCLK/8 rate. This bitstream, representing the analog input signal, is input to the antialiasing decimation filter. The decimation filter reduces the sample rate and increases the resolution. FUNCTIONAL DESCRIPTION—AFE Encoder Channel Each encoder channel consists of a signal conditioner, a switched capacitor PGA, and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which forms part of the sigma-delta ADC, also performs critical system-level filtering. Due to the high level of oversampling, the input antialias require- ments are reduced such that a simple single pole RC stage is sufficient to give adequate attenuation in the band of interest. Signal Conditioner Each analog channel has an independent signal conditioning block. This allows the analog input to be configured by the user depending on whether differential or single-ended mode is used. Programmable Gain Amplifier Each encoder section’s analog front end comprises a Switched Capacitor PGA that also forms part of the sigma-delta modulator. The SC sampling frequency is DMCLK/8. The PGA, whose programmable gain settings are shown in Table II, may be used to increase the signal level applied to the ADC from low output sources such as microphones, and can be used to avoid placing external amplifiers in the circuit. The input signal level to the sigma-delta modulator should not exceed the maximum input voltage permitted. The PGA gain is set by bits IGS0, IGS1, and IGS2 in control Registers D, E, and F. |
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