AD73460 datasheet(4/32 Pages) AD

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REV. 0

–4–

AD73460–SPECIFICATIONS

AD73460B

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC INPUTS

VINH, Input High Voltage

VDD – 0.8

VDD

VINL, Input Low Voltage

0.8

IIH, Input Current

µA

CIN, Input Capacitance

LOGIC OUTPUTS

VOH, Output High Voltage

VDD – 0.4

VDD

|IOUT|

≤ 100 µA

VOL, Output Low Voltage

0.4

|IOUT|

≤ 100 µA

Three-State Leakage Current

–10

+10

µA

POWER SUPPLIES

AVDD1, AVDD2

3.0

3.6

DVDD

3.0

3.6

IDD

See Table I

NOTES

1Operating temperature range is as follows: –20

°C to +85°C. Therefore, T

MIN = –20

°C and T

MAX = +85

°C.

2Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).

3At input to sigma-delta modulator of ADC.

4Guaranteed by design.

5Overall group delay will be affected by the sample rate and the external digital filtering.

6The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4

× 1011)/DMCLK.

7Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier

bypassed and input gain of 0 dB.

8Test Conditions: no load on digital inputs, analog inputs ac coupled to ground.

Specifications subject to change without notice.

Table I. AFE Section Current Summary (AVDD = DVDD = 3.3 V)

Total

Current

MCLK

Conditions

(Max)

Comments

REFCAP Only On

1.0

REFOUT Disabled

REFCAP and

REFOUT Only On

4.5

All Sections On

26.5

Yes

REFOUT Enabled

All Sections Off

1.5

Yes

MCLK Active Levels Equal to 0 V and DVDD

All Sections Off

0.1

Digital Inputs Static and Equal to 0 V or DVDD

The above values are in mA. MCLK = 16.384 MHz; SCLK = 16.384 MHz.

(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V,

fMCLK = 16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)

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