AD73460 datasheet(23/32 Pages) AD

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AD73460

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Interrupts

The interrupt controller allows the processor to respond to the

eleven possible interrupts and

RESET with minimum overhead.

The AD73460 provides four dedicated external interrupt

input pins,

IRQ2, IRQL0, IRQL1, and IRQE. In addition,

SPORT1 may be reconfigured for

IRQ0, IRQ1, FLAG_IN,

and FLAG_OUT, for a total of six external interrupts. The

AD73460 also supports internal interrupts from the timer, the

byte DMA port, the two serial ports, software and the power-down

control circuit. The interrupt levels are internally prioritized

and individually maskable (except power down and reset). The

IRQ2, IRQ0, and IRQ1 input pins can be programmed to be

either level- or edge-sensitive.

IRQL0 and IRQL1 are level-

sensitive and

IRQE is edge-sensitive. The priorities and vector

addresses of all interrupts are shown in Table XVII.

Table XVII. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

Source of Interrupt

Address (Hex)

RESET (or Power-Up with PUCR = 1) 0000 (Highest Priority)

Power-Down (Nonmaskable)

002C

IRQ2

0004

IRQL1

0008

IRQL0

000C

SPORT0 Transmit

0010

SPORT0 Receive

0014

IRQE

0018

BDMA Interrupt

001C

SPORT1 Transmit or

IRQ1

0020

SPORT1 Receive or

IRQ0

0024

Timer

0028 (Lowest Priority)

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially. Inter-

rupts can be masked or unmasked with the IMASK register.

Individual interrupt requests are logically ANDed with the bits

in IMASK; the highest priority unmasked interrupt is then

selected. The power-down interrupt is nonmaskable.

The AD73460 masks all interrupts for one instruction cycle

following the execution of an instruction that modifies the

IMASK register. This does not affect serial port autobuffering

or DMA transfers.

The interrupt control register, ICNTL, controls interrupt nest-

ing and defines the

IRQ0, IRQ1, and IRQ2 external interrupts

to be either edge- or level-sensitive. The

IRQE pin is an external

edge-sensitive interrupt and can be forced and cleared. The

IRQL0 and IRQL1 pins are external level-sensitive interrupts.

The IFC register is a write-only register used to force and clear

interrupts. On-chip stacks preserve the processor status and are

automatically maintained during interrupt handling. The stacks

are twelve levels deep to allow interrupt, loop and subroutine

nesting. The following instructions allow global enable or disable

servicing of the interrupts (including power-down), regardless of

the state of IMASK. Disabling the interrupts does not affect

serial port autobuffering or DMA.

ENA INTS;

DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The AD73460 has three low power modes that significantly

reduce the power dissipation when the device operates under

standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external

power dissipation.

Power-Down

The AD73460 processor has a low power feature that lets the

processor enter a very low power dormant state through hard-

ware or software control. Following is a brief list of power-down

features. Refer to the ADSP-2100 Family User’s Manual, Third

Edition, “System Interface” chapter, for detailed information

about the power-down feature.

• Quick recovery from power-down. The processor begins

executing instructions in as few as 400 CLKIN cycles.

• Support for an externally generated TTL or CMOS processor

clock. The external clock can continue running during power-

down without affecting the 400 CLKIN cycle recovery.

• Support for crystal operation includes disabling the oscillator

to save power (the processor automatically waits 4096 CLKIN

cycles for the crystal oscillator to start and stabilize), and

letting the oscillator run to allow 400 CLKIN cycle start up.

• Power-down is initiated by either the power-down pin (PWD)

or the software power-down force bit. Interrupt support allows

an unlimited number of instructions to be executed before

optionally powering down. The power-down interrupt can

also be used as a nonmaskable, edge-sensitive interrupt.

• Context clear/save control allows the processor to continue

where it left off or start with a clean context when leaving the

power-down state.

• The RESET pin can also be used to terminate power-down.

• Power-down acknowledge pin indicates when the processor

has entered power-down.

Idle

When the AD73460 is in the Idle Mode, the processor waits

indefinitely in a low power state until an interrupt occurs. When

an unmasked interrupt occurs, it is serviced; execution then con-

tinues with the instruction following the IDLE instruction. In

Idle Mode IDMA, BDMA, and autobuffer cycle steals still occur.

Slow Idle

The IDLE instruction on the AD73460 slows the processor’s

internal clock signal, further reducing power consumption. The

reduced clock frequency, a programmable fraction of the normal

clock rate, is specified by a selectable divisor given in the IDLE

instruction. The format of the instruction is

IDLE (n);

where n = 16, 32, 64, or 128. This instruction keeps the proces-

sor fully functional, but operating at the slower clock rate. While

it is in this state, the processor’s other internal clock signals,

such as SCLK, CLKOUT, and timer clock, are reduced by the

same ratio. The default form of the instruction, when no clock

divisor is given, is the standard IDLE instruction.

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