AD73460 datasheet(30/32 Pages) AD

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AD73460

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Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in

Figure 19. You must add this connector to your target board

design if you intend to use the EZ-ICE. Be sure to allow

enough room in your system to fit the EZ-ICE probe onto the

14-pin connector.

GND

KEY (NO PIN)

RESET

TOP VIEW

EBG

EBR

ELOUT

EINT

ELIN

ECLK

EMS

ERESET

Figure 19. Target Board Connector for EZ-ICE

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-

tion—you must remove Pin 7 from the header. The pins must

be 0.025 inch square and at least 0.20 inch in length. Pin spac-

ing should be 0.1

× 0.1 inches. The pin strip header must have

at least 0.15-inch clearance on all sides to accept the EZ-ICE

probe plug.

Pin strip headers are available from vendors such as 3M,

McKenzie, and Samtec.

Target Memory Interface

For your target system to be compatible with the EZ-ICE

emulator, it must comply with the memory interface guide-

lines listed below.

PM, DM, BM, IOM, and CM

Design your Program Memory (PM), Data Memory (DM),

Byte Memory (BM), I/O Memory (IOM), and Composite

Memory (CM) external interfaces to comply with worst-case

device timing requirements and switching characteristics as

specified in the DSP’s data sheet. The performance of the

EZ-ICE may approach published worst-case specification for

some memory access timing requirements and switching

characteristics.

Note: If your target does not meet the worst-case chip specifica-

tion for memory access parameters, you may not be able to

emulate your circuitry at the desired CLKIN frequency.

Depending on the severity of the specification violation, you

may have trouble manufacturing your system as DSP compo-

nents statistically vary in switching characteristic and timing

requirements within published limits.

Restriction: All memory strobe signals on the AD73460 (

RD,

WR, PMS, DMS, BMS, CMS, and IOMS) used in your target

system must have 10 k

Ω pull-up resistors connected when the

EZ-ICE is being used. The pull-up resistors are necessary

because there are no internal pull-ups to guarantee their state

during prolonged three-state conditions resulting from typical

EZ-ICE debugging sessions. These resistors may be removed at

your option when the EZ-ICE is not being used.

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some

system signals changes. Design your system to be compatible

with the following system interface signal changes introduced by

the EZ-ICE board:

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the

RESET

signal.

• EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the

BR signal.

• EZ-ICE emulation ignores RESET and BR when single-

stepping.

• EZ-ICE emulation ignores RESET and BR when in Emulator

Space (DSP halted).

• EZ-ICE emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the

DSP’s external memory bus only if bus grant (

BG) is asserted

by the EZ-ICE board’s DSP.

ANALOG FRONT END (AFE) INTERFACING

The AFE section of the AD73460 features six input channels

each with 16-bit linear resolution. Connectivity to the AFE

section from the DSP is uncommitted thus allowing the user the

flexibility of connecting in the mode or configuration of their

choice. This section will detail several configurations—with no

extra AFE channels configured and with an extra AFE section

configured (using an external AD73360 AFE).

DSP SPORT TO AFE INTERFACING

The SCLK, SDO, SDOFS, SDI, and SDIFS must be connected

to the SCLK, DR, RFS, DT, and TFS pins of the DSP respec-

tively. The SE pin may be controlled from a parallel output pin

or flag pin such as FL0–2 or, where SPORT power-down is not

required, it can be permanently strapped high using a suitable

pull-up resistor. For consistent performance the SE pin should

be synchronized to the rising edge of the AMCLK using a cir-

cuit similar to that of Figure 23. The

ARESET pin may be

connected to the system hardware reset structure or it may also

be controlled using a dedicated control line. In the event of

tying it to the global system reset, it is necessary to operate the

device in mixed mode, which allows a software reset, otherwise

there is no convenient way of resetting the device.

TFS

SCLK

RFS

DSP

SECTION

AFE

SECTION

SDIFS

SDI

SCLK

SDO

SDOFS

FL0

FL1

ARESET

Figure 20. DSP to AD73460 AFE Connection

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