AD73460 datasheet(12/32 Pages) AD

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AD73460

–12–

Analog Sigma-Delta Modulator

The AD73460 input channels employ a sigma-delta conversion

technique, which provides a high resolution 16-bit output with

system filtering being implemented on-chip.

Sigma-delta converters employ a technique known as over-

sampling, where the sampling rate is many times the highest

frequency of interest. In the case of the AD73460, the initial

sampling rate of the sigma-delta modulator is DMCLK/8. The

main effect of oversampling is that the quantization noise is

spread over a very wide bandwidth, up to fS/2 = DMCLK/16

(Figure 3a). This means that the noise in the band of interest is

much reduced. Another complementary feature of sigma-delta

converters is the use of a technique called noise-shaping. This

technique has the effect of pushing the noise from the band of

interest to an out-of-band position (Figure 3b). The combina-

tion of these techniques, followed by the application of a digital

filter, reduces the noise in band sufficiently to ensure good

dynamic performance from the part (Figure 3c).

BAND

INTEREST

fS/2

DMCLK/16

fS/2

DMCLK/16

NOISE-SHAPING

BAND

INTEREST

fS/2

DMCLK/16

DIGITAL FILTER

BAND

INTEREST

Figure 3. Sigma-Delta Noise Reduction

Figure 4 shows the various stages of filtering that are employed

in a typical AD73460 application. In Figure 4a we see the trans-

fer function of the external analog antialias filter. Even though it

is a single RC pole, its cutoff frequency is sufficiently far away

from the initial sampling frequency (DMCLK/8) that it takes

care of any signals that could be aliased by the sampling frequency.

This also shows the major difference between the initial over-

sampling rate and the bandwidth of interest. In Figure 4b, the

signal and noise-shaping responses of the sigma-delta modulator

are shown. The signal response provides further rejection of any

high frequency signals while the noise-shaping will push the inher-

ent quantization noise to an out-of-band position. The detail of

Figure 4c shows the response of the digital decimation filter

(Sinc-cubed response) with nulls every multiple of DMCLK/256,

which is the decimation filter update rate. The final detail in

Figure 4d shows the application of a final antialias filter in the

DSP engine. This has the advantage of being implemented accord-

ing to the user’s requirements and available MIPS. The filtering

in Figures 4a through 4c is implemented in the AD73460.

B = 4kHz

SINIT = DMCLK/8

a. Analog Antialias Filter Transfer Function

B = 4kHz

SINIT = DMCLK/8

NOISE TRANSFER FUNCTION

SIGNAL TRANSFER FUNCTION

b. Analog Sigma-Delta Modulator Transfer Function

B = 4kHz

SINTER = DMCLK/256

c. Digital Decimator Transfer Function

B = 4kHz

SINTER = DMCLK/256

fSFINAL = 8kHz

d. Final Filter LPF (HPF) Transfer Function

Figure 4. DC Frequency Responses

Decimation Filter

The digital filter used in the AD73460 carries out two important

functions. Firstly, it removes the out-of-band quantization noise,

which is shaped by the analog modulator and secondly, it deci-

mates the high frequency bitstream to a lower rate 15-bit word.

The antialiasing decimation filter is a sinc-cubed digital filter

that reduces the sampling rate from DMCLK/8 to DMCLK/256,

and increases the resolution from a single bit to 15 bits. Its Z

transform is given as: [(1–Z

–32)/(1–Z–1)]3. This ensures a mini-

mal group delay of 25

µs.

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