AD7712 datasheet(6/28 Pages) AD

6 / 28 page

REV. E

–6–

AD7712

Limit at TMIN, TMAX

Parameter

(A, S Versions)

Units

Conditions/Comments

External Clocking Mode

fSCLK

fCLK IN/5

MHz max

Serial Clock Input Frequency

t20

ns min

DRDY to RFS Setup Time

t21

ns min

DRDY to RFS Hold Time

t22

× t

CLK IN

ns min

A0 to

RFS Setup Time

t23

ns min

A0 to

RFS Hold Time

t24

× t

CLK IN

ns max

Data Access Time (

RFS Low to Data Valid)

t25

ns min

SCLK Falling Edge to Data Valid Delay

× t

CLK IN + 20

ns max

t26

× t

CLK IN

ns min

SCLK High Pulse Width

t27

× t

CLK IN

ns min

SCLK Low Pulse Width

t28

tCLK IN + 10

ns max

SCLK Falling Edge to

DRDY High

t29

ns min

SCLK to Data Valid Hold Time

tCLK IN + 10

ns max

t30

ns min

RFS/TFS to SCLK Falling Edge Hold Time

t31

× t

CLK IN/2 + 50

ns max

RFS to Data Valid Hold Time

t32

ns min

A0 to

TFS Setup Time

t33

ns min

A0 to

TFS Hold Time

t34

× t

CLK IN

ns min

SCLK Falling Edge to

TFS Hold Time

t35

× t

CLK IN – SCLK High

ns min

Data Valid to SCLK Setup Time

t36

ns min

Data Valid to SCLK Hold Time

NOTES

1Guaranteed by design, not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input

signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2See Figures 11 to 14.

3The AD7712 is specified with a 10 MHz clock for AV

DD voltages of +5 V

± 5%. It is specified with an 8 MHz clock for AV

DD voltages greater than 5.25 V and less

than 10.5 V.

4CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7712 is not in STANDBY mode. If no clock is present in this case, the

device can draw higher current than specified and possibly become uncalibrated.

5The AD7712 is production tested with f

CLK IN at 10 MHz (8 MHz for AVDD < +5.25 V). It is guaranteed by characterization to operate at 400 kHz.

6Specified using 10% and 90% points on waveform of interest.

7These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

8These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number

is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are

the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

Specifications subject to change without notice.

TO OUTPUT

+2.1V

1.6mA

200 A

100pF

Figure 1. Load Circuit for Access Time and Bus Relinquish

Time

PIN CONFIGURATION

DIP AND SOIC

TOP VIEW

(Not to Scale)

AD7712

AVDD

VSS

STANDBY

AIN1(–)

MCLK IN

MCLK OUT

AIN1(+)

MODE

SCLK

SYNC

VBIAS

REF IN(–)

REF IN(+)

REF OUT

AIN2

DGND

DVDD

SDATA

DRDY

AGND

TFS

RFS

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