AD7715

–5–

REV. C

Parameter

(A Version)

Unit

Conditions/Comments

3, 4

400

kHz min

Master Clock Frequency: Crystal Oscillator or Externally Supplied

2.5

MHz max

for Specified Performance

0.4

× t

CLK IN

ns min

0.4

× t

CLK IN

ns min

Master Clock Input High Time

500

× t

CLK IN

ns nom

DRDY High Time

100

ns min

RESET Pulsewidth

Read Operation

0

ns min

DRDY to CS Setup Time

120

ns min

CS Falling Edge to SCLK Rising Edge Setup Time

5

0

ns min

SCLK Falling Edge to Data Valid Delay

80

ns max

100

ns max

100

ns min

SCLK High Pulsewidth

100

ns min

SCLK Low Pulsewidth

0

ns min

CS Rising Edge to SCLK Rising Edge Hold Time

6

10

ns min

Bus Relinquish Time after SCLK Rising Edge

60

ns max

100

ns max

100

ns max

SCLK Falling Edge to

Write Operation

120

ns min

CS Falling Edge to SCLK Rising Edge Setup Time

30

ns min

Data Valid to SCLK Rising Edge Setup Time

20

ns min

Data Valid to SCLK Rising Edge Hold Time

100

ns min

SCLK High Pulsewidth

100

ns min

SCLK Low Pulsewidth

0

ns min

CS Rising Edge to SCLK Rising Edge Hold Time

NOTES

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of D V

device can draw higher current than specified and possibly become uncalibrated.

then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the

true bus relinquish times of the part and as such are independent of external bus loading capacitances.

7

DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care

should be taken that subsequent reads do not occur close to the next output update.

Specifications subject to change without notice.

TO

OUTPUT

PIN

+1.6V

50pF

Figure 1. Load Circuit for Access Time and Bus Relinquish Time