AD7715 datasheet(25/31 Pages) AD

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AD7715

–25–

REV. C

AD7715 to 8XC51 Interface

An interface circuit between the AD7715 and the 8XC51

microcontroller is shown in Figure 10. The diagram shows the

minimum number of interface connections with

CS on the

AD7715 hardwired low. In the case of the 8XC51 interface, the

minimum number of interconnects is just two. In this scheme,

the

DRDY bit of the Communications Register is monitored to

determine when the Data Register is updated. The alternative

scheme, which increases the number of interface lines to three,

is to monitor the

DRDY output line from the AD7715. The

monitoring of the

DRDY line can be done in two ways. First,

DRDY can be connected to one of the 8XC51’s port bits (such

as P1.0) which is configured as an input. This port bit is then

polled to determine the status of

DRDY. The second scheme is

to use an interrupt driven system in which case, the

DRDY

output is connected to the

INT1 input of the 8XC51. For inter-

faces that require control of the

CS input on the AD7715, one

of the port bits of the 8XC51 (such as P1.1), which is config-

ured as an output, can be used to drive the

CS input.

The 8XC51 is configured in its Mode 0 serial interface mode.

Its serial interface contains a single data line. As a result, the

DATA OUT and DATA IN pins of the AD7715 should be

connected together with a 10 k

Ω pull-up resistor. The serial

clock on the 8XC51 idles high between data transfers. The

8XC51 outputs the LSB first in a write operation while the

AD7715 rearranged before being written to the output serial

read operation while the 8XC51 expects the LSB first. There-

fore, the data which is read into the serial buffer needs to be

rearranged before the correct data word from the AD7715 is

available in the accumulator.

AD7715

DATA OUT

8XC51

RESET

DATA IN

SCLK

P3.0

P3.1

DVDD

10k

Figure 10. AD7715 to 8XC51 Interface

AD7715 to ADSP-2103/ADSP-2105 Interface

Figure 11 shows an interface between the AD7715 and the

ADSP-2103/ADSP-2105 DSP processor. In the interface

shown, the

DRDY bit of the Communications Register is again

monitored to determine when the Data Register is updated. The

alternative scheme is to use an interrupt driven system, in which

case the

DRDY output is connected to the IRQ2 input of the

ADSP-2103/ADSP-2105. The serial interface of the ADSP-

2103/ADSP-2105 is set up for alternate framing mode. The

RFS and TFS pins of the ADSP-2103/ADSP-2105 are config-

ured as active low outputs, and the ADSP-2103/ADSP-2105

serial clock line, SCLK, is also configured as an output. The

for the AD7715 is active when either the

RFS or TFS outputs

from the ADSP-2103/ADSP-2105 are active. The serial clock

rate on the ADSP-2103/ADSP-2105 should be limited to

3 MHz to ensure correct operation with the AD7715.

AD7715

DATA OUT

ADSP-2103/2105

RESET

DATA IN

SCLK

RFS

DVDD

TFS

SCLK

Figure 11. AD7715 to ADSP-2103/ADSP-2105 Interface

CODE FOR SETTING UP THE AD7715

Table XVI gives a set of read and write routines in C code for

interfacing the 68HC11 microcontroller to the AD7715. The

sample program sets up the various registers on the AD7715

and reads 1000 samples from the part into the 68HC11. The

setup conditions on the part are exactly the same as those out-

lined for the flowchart of Figure 8. In the example code given

here, the

DRDY output is polled to determine if a new valid

word is available in the data register.

The sequence of the events in this program are as follows:

1. Write to the Communications Register, setting the gain to 1

with standby inactive.

2. Write to the Setup Register, setting bipolar mode, buffer off,

no filter synchronization, confirming a clock frequency of

2.4576 MHz, setting the output rate for 60 Hz and initiating

a self-calibration.

3. Poll the

DRDY Output.

4. Read the data from the Data Register.

5. Loop around doing Steps 3 and 4 until the specified number

of samples have been taken.

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