AD8309 datasheet(12/20 Pages) AD

12 / 20 page

REV. B

AD8309

–12–

A fully-programmable output interface is provided for the hard-

limited signal, permitting the user to establish the optimal output

current from its differential current-mode output. Its magnitude

is determined by the resistor RLIM placed between LMDR (Pin

9) and ground, across which a nominal bias voltage of ~400 mV

appears. Using RLIM = 200

Ω, this dc bias current, which is

commutated alternately to the output pins, LMHI and LMLO,

by the signal, is 2 mA. (The total supply current is somewhat

higher).

These currents may readily be converted to voltage form by the

inclusion of load resistors, which will typically range from a few

tens of ohms at 500 MHz to as high as 2 k

Ω in lower frequency

applications. Alternatively, a resonant load may be used to ex-

tract the fundamental signal and modulation sidebands, mini-

mizing the out-of-band noise. A transformer or impedance

matching network may also be used at this output. The peak

voltage swing down from the supply voltage may be 1.2 V, be-

fore the output transistors go into saturation. (The Applications

section provides further information on the use of this interface).

The supply current for all sections except the limiter output

stage, and with no load attached to the RSSI output, is nomi-

nally 16 mA at TA = 27

°C, substantially independent of supply

voltage. It varies in direct proportion to the absolute tempera-

ture (PTAT). The RSSI load current is simply the voltage at

VLOG divided by the load resistance (e.g., 2.4 mA max in a

1 k

Ω load). The limiter supply current is 1.1 times that flowing

in RLIM. The AD8309 may be enabled/disabled by a CMOS-

compatible level at ENBL (Pin 8).

In the following simplified interface diagrams, the components

denoted with an uppercase “R” are thin-film resistors having a

very low temperature-coefficient of resistance and high linearity

under large-signal conditions. Their absolute value is typically

within

±20%. Capacitors denoted using an uppercase “C” have

a typical tolerance of

±15% and essentially zero temperature or

voltage sensitivity. Most interfaces have additional small junc-

tion capacitances associated with them, due to active devices or

ESD protection; these may be neither accurate nor stable. Com-

ponent numbering in each of these interface diagrams is local.

Enable Interface

The chip-enable interface is shown in Figure 26. The current in

R1 controls the turn-on and turn-off states of the band-gap

reference and the bias generator, and is a maximum of 100

µA

when Pin 8 is taken to 5 V. Left unconnected, or at any voltage

below 1 V, the AD8309 will be disabled, when it consumes a

sleep current of much less than 1

µA (leakage currents only); when

tied to the supply, or any voltage above 2 V, it will be fully en-

abled. The internal bias circuitry requires approximately 300 ns

for either OFF or ON, while a delay of some 6

µs is required for

the supply current to fall below 10

µA.

1.3k

50k

COMM

ENBL

60k

TO BIAS

ENABLE

Figure 26. Enable Interface

Input Interface

Figure 27 shows the essentials of the signal input interface. The

parasitic capacitances to ground are labeled CP; the differential

input capacitance, CD, mainly due to the diffusion capacitance

of Q1 and Q2. In most applications both input pins are ac-

coupled. The switch S closes when Enable is asserted. When

disabled, the inputs float, bias current IE is shut off, and the

coupling capacitors remain charged. If the log amp is disabled

for long periods, small leakage currents will discharge these

capacitors. If they are poorly matched, charging currents at

power-up can generate a transient input voltage which may

block the lower reaches of the dynamic range until it has be-

come much less than the signal.

In most applications, the input signal will be single-sided, and

may be applied to either Pin 4 or 5, with the remaining pin ac-

coupled to ground. Under these conditions, the largest input

signal that can be handled is –3 dBV (sine amplitude of 1 V)

when operating from a 3 V supply ; a +3 dBV input may be

handled using a supply of 4.5 V or greater. When using a fully-

balanced drive, the +3 dBV level may be achieved for the sup-

plies down to 2.7 V and +9 dBV using >4.5 V. For frequencies

in the range 10 MHz to 200 MHz these high drive levels are

easily achieved using a matching network (see later). Using such

a network, having an inductor at the input, the input transient is

eliminated.

RIN = 1k

SIGNAL

INPUT

INLO

INHI

VPS1

COMM

1.78V

3.65k

1.725V

2.5pF

IB = 15mA

(TOP-END

DETECTORS)

2.6k

RIN = 3k

20e

130

3.4mA

PTAT

GAIN BIAS

1.26V

TO STAGES

1 THRU 5

TO 2ND

STAGE

Figure 27. Signal Input Interface

Limiter Output Interface

The simplified limiter output stage is shown in Figure 28. The

bias for this stage is provided by a temperature-stable reference

voltage of nominally 400 mV which is forced across the external

resistor RLIM connected from Pin 9 (LMDR, or limiter drive) by

a special op amp buffer stage. The biasing scheme also intro-

duces a slight “lift” to this voltage to compensate for the finite

current gain of the current source Q3 and the output transistors

Q1 and Q2. A maximum current of 10 mA is permissible (RLIM

= 40

Ω). In special applications, it may be desirable to modulate

the bias current; an example of this is provided in the Applica-

tions section. Note that while the bias currents are temperature

stable, the ac gain of this stage will vary with temperature, by

–6 dB over a 120

°C range.

A pair of supply and temperature stable complementary currents

is generated at the differential output LMHI and LMLO (Pins

12 and 13), having a square wave form with rise and fall times

of typically 0.4 ns, when load resistors of 50

Ω are used. The

voltage at these output pins may swing to 1.2 V below the sup-

ply voltage applied to VPS2 (Pin 15).

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