REV. B

AD8309

–19–

Table IV. Evaluation Board Setup Options

Component

Function

Default Condition

SW1

SW1 = A

AD8309 is in normal operating mode. In position B, the ENBL pin is connected

to an SMA connector labeled Ext Enable. An applied signal can be applied to this

connector to enable/disable the AD8309. If left open, the ENBL pin will float to

ground putting the device in power-down mode.

R1

This pad is used to ac-couple to ground for single-ended input drive. To drive the

R1 = 0

Ω

AD8309 differentially, R1 should be removed.

R/L, C1, C2

Input Interface. The 52.3

Ω resistor in position R/L along with C1 and C2 create

R/L= 52.3

Ω

a high pass input filter whose corner frequency (640 kHz) is equal to 1/(

πRC),

C1 = C2 = 0.01

µF

where C = C1 = C2 and R is the parallel combination of 52.3

Ω and the AD8309’s

input impedance of 1000

Ω. Alternatively, the 52.3 Ω resistor can be replaced by

an inductor to form an input matching network. See Input Matching Network

section for more details.

R3/R4

Slope Adjust. A simple slope adjustment can be implemented by adding a resistive

R3 = 0

Ω

divider at the VLOG output. R3 and R4, whose sum should be about 1 k

Ω, and

R4 =

never less than 40

Ω (see specs), set the slope according to the equation:

Slope = 20 mV/dB

× R4/(R3+R4).

L1, C5, C6

Limiter Output Coupling. C5 and C6 ac-couple the limiter’s differential outputs.

L1 = Open

By adjusting these values and installing an inductor in L1, an output matching

C5 = 0.01

µF

network can be implemented.

C6 = 0.01

µF

R8, LK1

Limiter Output Current. With LK2 installed, R8 enables and sets the limiter

LK1 Installed. R8 = 402

Ω

output current. The limiter’s output current is set according to the equation

To disable the limiter (recommended if the limiter is not being used), LK3 should

be removed.

C7

RSSI Bandwidth Adjust. The addition of C7 will lower the RSSI bandwidth of the

C7 = Open

Figure 41. Layout of Signal Layer

Figure 42. Layout of Power Layer