AD8309 datasheet(13/20 Pages) AD

13 / 20 page

REV. B

AD8309

–13–

Because of the very high gain bandwidth product of this ampli-

fier considerable care must be exercised in using the limiter

outputs. The minimum necessary bias current and voltage

swings should be used. These outputs are best utilized in a fully-

differential mode. A flux-coupled transformer, a balun, or an

output matching network can be selected to transform these

voltages to a single-sided form. Equal load resistors are recom-

mended, even when only one output pin is used, and these

should always be returned to the same well decoupled node on

the PC board. When the AD8309 is used only to generate an

RSSI output, the limiter should be completely disabled by omit-

ting RLIM and strapping LMHI and LMLO to VPS2.

VPS2

LMHI

LMLO

COM1

LMDR

RLIM

2.6k

1.3k

FROM FINAL

LIMITER STAGE

400mV

ZERO-TC

Figure 28. Limiter Output Interface

RSSI Output Interface

The outputs from the ten detectors are differential currents,

having an average value that is dependent on the signal input

level, plus a fluctuation at twice the input frequency. The cur-

rents are summed at the internal nodes LGP and LGN shown in

Figure 29. A further current ITC is added to LGP, to position

the intercept to –108 dBV, by raising the RSSI output voltage

for zero input, and to provide temperature compensation , re-

sulting in a stable intercept. For zero signal conditions, all the

detector output currents are equal. For a finite input, of either

polarity, their difference is converted by the output interface to

a single-sided voltage nominally scaled 20 mV/dB (400 mV per

decade), at the output VLOG (Pin 16). This scaling is con-

trolled by a separate feedback stage, having a tightly controlled

transconductance. A small uncertainty in the log slope and

intercept remains (see Specifications); the intercept may be

adjusted (see Applications).

VPS2

FLTR

VLOG

20mV/dB

COMM

ISOURCE

>50mA

ON DEMAND

3.5pF

CURRENT

MIRROR

ISINK

FIXED

1mA

3.3k

125 A

1.3k

VLOG

TRANSCONDUCTANCE

DETERMINES SLOPE

LGP

LGN

SUMMED

DETECTOR

OUTPUTS

250 s

Figure 29. Simplified RSSI Output Interface

The RSSI output bandwidth, fLP, is nominally 3.5 MHz. This is

controlled by the compensation capacitor C1, which may be

increased by adding an external capacitor, CF, between FLTR

(Pin 10) and VLOG (Pin 16). An external 33 pF will reduce fLP

to 350 kHz, while 360 pF will set it to 35 kHz, in each case with

an essentially one-pole response. In general, the relationships

are:

CpF

−

12 7 10

–.

;

–

(7)

Using a load resistance of 50

Ω or greater, and at any tempera-

ture, the peak output voltage may be at least 2.4 V when using a

supply of 4.5 V, and at least 2.1 V for a 3 V supply, which are

consistent with the maximum permissible input levels. The incre-

mental output resistance is approximately 0.3

Ω at low frequen-

cies, rising to 1

Ω at 150 kHz and 18 Ω at very high frequencies.

The output is unconditionally stable with load capacitance, but

it should be noted while the peak sourcing current is over 100 mA,

and able to rapidly charge even large capacitances, the internally

provided sinking current is only 1 mA. Thus, the fall time from

the 2 V level will be as long as 2

µs for a 1 nF load. This may be

reduced by adding a grounded load resistance.

USING THE AD8309

The AD8309 exhibits very high gain from 1 MHz to over 1 GHz,

at which frequency the gain of the main path is still over 65 dB.

Consequently, it is susceptible to all signals within this very

broad frequency range which find their way to the input termi-

nals. It is important to remember that these are quite indistin-

guishable from the “wanted” signal, and will have the effect of

raising the apparent noise floor (that is, lowering the useful

dynamic range). Therefore, while the signal of interest may be

an IF of, say, 200 MHz, any of the following could easily be

larger than this signal at the lower extremities of its dynamic

range: a 60 Hz hum, picked up due to poor grounding tech-

niques; spurious coupling from digital logic on the same PC

board; a strong EMI source; etc.

Very careful shielding is essential to guard against such un-

wanted signals, and also to minimize the likelihood of instability

due to HF feedback from the limiter outputs to the input. With

this in mind, the minimum possible limiter gain should be used.

Where only the logarithmic amplifier (RSSI) function is re-

quired, the limiter should be disabled by omitting RLIM and

tying the outputs LMHI and LMLO directly to VPS2.

A good ground plane should be used to provide a low imped-

ance connection to the common pins, for the decoupling

capacitor(s) used at VPS1 and VPS2, and at the output ground.

It is inadvisable to assume that any ground plane is an equipo-

tential, however, and neither of the signal inputs should be ac-

coupled directly to it, but kept separate, being returned instead

to the “low” associated with the source. This requires isolating

the “low”’ side of an input connector with a small resistance to

the ground plane. Note that COM2 is a special ground pin

serving just the RSSI output.

The voltages at the two supply pins should not be allowed to

differ greatly; up to 500 mV is permissible It is desirable to

allow VPS1 to be slightly more negative than VPS2. When the

primary supply is greater than 2.7 V, the decoupling resistors R1

and R2 may be increased to improve the isolation and lower

dissipation in the IC. However, since VPS2 supports the RSSI

AD8309 Datasheet(PDF) 13 Page - Analog Devices

AD8309 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL