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L9313 Datasheet(PDF) 7 Page - Agere Systems |
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L9313 Datasheet(HTML) 7 Page - Agere Systems |
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7 / 40 page ![]() Data Sheet September 2001 Full-Feature SLIC and Ringing Relay for TR-57 Applications L9313 Line Interface and Line Access Circuit Agere Systems Inc. 7 Description (continued) The L9313 uses a voltage feed, current sense architec- ture; thus, the transmit gain is a transconductance. The L9313 transconductance is set via a single external resistor, and this device is designed for optimal perfor- mance with a transconductance set at 300 V/A. The L9313 offers an option for a single-ended to differ- ential receive gain of either 8 or 2. These options are mask programmable at the factory and are selected by choice of part number. A receive gain of 8 is more appropriate when choosing a first-generation type codec where termination imped- ance, hybrid balance, and overall gains are set by external analog filters. The higher gain is typically required for synthesization of complex termination impedance. A receive gain of 2 is more appropriate when choosing a third-generation type codec. Third-generation codecs will synthesize termination impedance, set hybrid bal- ance, and set overall gains. To accomplish these func- tions, third-generation codecs typically have both analog and digital gain filters. For optimal signal-to- noise performance, it is best to operate the codec at a higher gain level. If the SLIC then provides a high gain, the SLIC output may be saturated causing clipping dis- tortion of the signal at tip and ring. To avoid this situa- tion, with a higher-gain SLIC, external resistor dividers are used. These external components are not neces- sary with the lower gain offered by the L9313. The RCVP/RCVN SLIC inputs are floating inputs. If there is not feedback from RCVP/RCVN to VITR, RCVP/RCVN may be directly coupled to the codec out- put. If there is feedback, RCVP/RCVN must be ac-cou- pled to the codec output. This device is packaged in a 44-pin PLCC surface- mount package. Architecture 12-3523f (F) Figure 1. Architecture Diagram – + AAC + – AX 2.35 V BANDGAP REFERENCE RFT TIP/RING CURRENT SENSE BGND ITR/325 VITR RFR VBAT BGND VBAT ITR ITR RING TRIP DETECTOR SCAN & RING GND DETECTOR SCAN CLAMP SCAN VBAT BGND RT ILC ac INTERFACE x1 x1 SWITCHHOOK WINDOW COMPARATOR IN REF CF2 CURRENT LIMITER AND INRUSH CONTROL CF2 REF PARALLEL DATA INTERFACE VREF TXI ITR TRNG PT PR RTS RSW RRING VTX VCC AGND RGDET ICM VBAT2/PWR VBAT VBAT1 VBAT1 BGND BGND RCVN FB1 CF2 FB2 FBRB dc ac DGND VDD VPROG B0 B1 B2 LATCH RESET LCTH LCF VITR CONTROL RT ILC FB RB VTX IN +5VD (1 V/50 mA) SW3 SW1 18 Ω 60 Ω SW2 18 Ω +5VA VBAT VBAT BGND BGND + – OUT AT + – OUT AR FB NSTAT 2.35 V VREF SW4 15 Ω RCVP OVH CF1 |
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