SPRUG18 datasheet(58/214 Pages) TI

58 / 214 page

32KB L1P

Memory Controller (PMC) with

Memory Protect/Bandwidth Mgmt

C64x+ DSP Core

Instruction Fetch

16-/32-bit Instruction Dispatch

Control Registers

In-Circuit Emulation

Instruction Decode

Data Path A

Data Path B

A31 - A16

A15 - A0

A Register File

B Register File

B31 - B16

B15 - B0

Boot

Controller

LPSC

PLLC

GPSC

.L1

.S1

.M1

.D1

.D2

.M2

.S2

.L2

32KB L1D

DMA Switch

Fabric

CFG Switch

Fabric

L2 Cache/

SRAM

1024 KB

Data Memory Controller (DMC) with

Memory Protect/Bandwidth Mgmt

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

www.ti.com

C64x+ Megamodule

5.1

Megamodule Diagram

The C64x+ Megamodule consists of several components - the C64x+ CPU and associated C64x+

Megamodule core, level-one and level-two memories (L1P, L1D, L2), data trace formatter (DTF),

embedded trace buffer (ETB), the interrupt controller, power-down controller, external memory controller

and a dedicated power/sleep controller (LPSC). The C64x+ Megamodule also provides support for

memory protection and bandwidth management (for resources local to the C64x+ Megamodule).

Figure 5-1 provides a block diagram of the C64x+ Megamodule.

Figure 5-1. C64x+ Megamodule Block Diagram

C64x+ Megamodule

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SPRUG18 Datasheet(PDF) 58 Page - Texas Instruments

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