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SPRUG18 Datasheet(PDF) 204 Page - Texas Instruments

Part # SPRUG18
Description  TMS320C6474 Multicore Digital Signal Processor
PDF  214 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SPRUG18 Datasheet(HTML) 204 Page - Texas Instruments

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TMS320C6474
SPRS552H
– OCTOBER 2008 – REVISED APRIL 2011
www.ti.com
7.23 Frame Synchronization
Frame synchronization handles timing and time alignment on the device by coordinating timing between
the DSP cores. Up to 30 programmable events based on RP3 or system timer. One output is used for
exporting frame alignment to aid in synchronizing external components.
Frame synchronization assists with synchronization of clock inputs:
•
OBSAI RP1 compliant input for frame burst data.
•
UMTS frame synchronization boundary used as an alternative to RP1 for frame burst data.
•
System timer synchronization used as an alternative to RP1.
The user may select between the OBSAI RP1-compliant FSYNCCLK(P|N) and FRAMEBURST(P|N)
signals or the alternate, single-ended ALTFSYNCCLK and ALTFSYNCPULSE inputs to drive the timers.
Table 7-90. FSYNC Event Connections
C64x+
C64x+
C64x+
MODULE EVENTS
MEGAMODULE
MEGAMODULE
MEGAMODULE
CIC0
CIC1
CIC2
TPCC
CIC3
TIMER
AIF
CORE 0
CORE 1
CORE 2
FSEVT0
X
X
X
X
FSEVT1
X
X
X
X
X
FSEVT2
X
X
X
X
X
FSEVT3
X
X
X
X
X
FSEVT4
X
X
X
X
FSEVT5
X
X
X
X
FSEVT6
X
X
X
X
FSEVT7
X
X
X
X
FSEVT8
X
X
X
X
FSEVT9
X
X
X
X
FSEVT10
X
X
X
X
FSEVT11
X
X
X
X
FSEVT12
X
X
X
X
FSEVT13
X
X
X
X
FSEVT14
X
X
X
X
FSEVT15
X
X
X
X
FSEVT16
X
X
X
X
FSEVT17
X
X
X
X
FSEVT18
X
X
X
X
X
FSEVT19
X
X
X
X
X
FSEVT20
X
X
X
X
X
FSEVT21
X
X
X
X
X
FSEVT22
X
X
X
X
X
FSEVT23
X
X
X
X
X
FSEVT24
X
X
X
X
FSEVT25
X
X
X
X
FSEVT26
X
X
X
X
FSEVT27
X
X
X
X
FSEVT28
X
X
X
X
FSEVT29
X
X
X
X
FS_ERR_Alarm0
X
X
X
FS_ERR_Alarm1
X
X
X
FS_AIFFrameSync
X
204
Peripheral Information and Electrical Specifications
Copyright
© 2008–2011, Texas Instruments Incorporated
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Product Folder Link(s) :TMS320C6474



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