ADV7182 datasheet(16/96 Pages) AD

16 / 96 page

ADV7182

Data Sheet

Rev. A | Page 16 of 96

GLOBAL CONTROL REGISTERS

POWER-SAVING MODES

Power-Down

PWRDWN, Address 0x0F[5]

The ADV7182 can be placed into a chip-wide, power-down mode

by setting the PWRDWN bit or by using the PWRDWN pin.

The power-down mode stops the clock from entering the digital

section of the chip, thereby freezing its operation. No I2C bits are

lost during power-down mode. The PWRDWN bit also affects

the analog blocks and switches them into low current modes.

The I2C interface is unaffected and remains operational in

power-down mode.

When PWRDWN is 0, the chip is operational. When PWRDWN is

1 (default), the ADV7182 is in a chip-wide, power-down mode.

RESET CONTROL

Reset, Chip Reset, Address 0x0F[7]

Setting this bit, which is equivalent to controlling the RESET

pin on the ADV7182, issues a full chip reset. All I2C registers are

reset to their default/power-up values. Note that some register bits

do not have a reset value specified. They keep their last written

value. Those bits are marked as having a reset value of x in the

sequence, the part immediately starts to acquire the incoming

video signal.

After setting the reset bit (or initiating a reset via the RESET pin),

the part returns to the default for its primary mode of operation.

All I2C bits are loaded with their default values, making this bit

self-clearing. Executing a software reset takes approximately 2 ms.

However, it is recommended to wait 5 ms before any further I2C

writes are performed.

The I2C master controller receives a no acknowledge condition

on the ninth clock cycle when chip reset is implemented (see

the MPU Port Description section).

When the reset bit is 0 (default), operation is normal.

When the reset bit is 1, the reset sequence starts.

GLOBAL PIN CONTROL

Tristate Output Drivers

TOD, Address 0x03[6]

This bit allows the user to tristate the output drivers of the ADV7182.

Upon setting the TOD bit, the P7 to P0, HS, and VS/FIELD/SFL

pins are tristated.

The timing pins (HS and VS/FIELD/SFL pins) can be forced active

via the TIM_OE bit. For more information on tristate control, see the

Tristate LLC Driver and the Timing Signals Output Enable sections.

Individual drive strength controls are provided via the

DR_STR_x bits.

When TOD is 0 (default), the output drivers are enabled.

When TOD is 1, the output drivers are tristated.

Tristate LLC Driver

TRI_LLC, Address 0x1D[7]

This bit allows the output drivers for the LLC pin of the ADV7182

to be tristated. For more information on tristate control, refer to the

Tristate Output Drivers and Timing Signals Output Enable sections.

Individual drive strength controls are provided via the

DR_STR_x bits.

When TRI_LLC is 0 (default), the LLC pin drivers work according

to the DR_STR_C[1:0] setting (pin enabled).

When TRI_LLC is 1, the LLC pin drivers are tristated.

Timing Signals Output Enable

TIM_OE, Address 0x04[3]

The TIM_OE bit should be regarded as an addition to the TOD bit.

Setting it high forces the output drivers for HS, VS/FIELD/SFL into

the active state (that is, driving state) even if the TOD bit is set. If

TIM_OE is set to low, the HS and VS/FIELD/SFL pins are tristated

depending on the TOD bit. This functionality is beneficial if the

decoder is used only as a timing generator. This may be the case

if only the timing signals are extracted from an incoming signal or

if the part is in free-run mode, where a separate chip can output

a company logo, for example.

For more information on tristate control, see the Tristate

Output Drivers and Tristate LLC Driver sections.

Individual drive strength controls are provided via the

DR_STR_x bits.

When TIM_OE is 0 (default), HS and VS/FIELD/SFL are tristated

according to the TOD bit.

When TIM_OE is 1, HS and VS/FIELD/SFL are forced active all

the time.

ADV7182 Datasheet(PDF) 16 Page - Analog Devices

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