ADV7182 datasheet(3/96 Pages) AD

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Data Sheet

ADV7182

Rev. A | Page 3 of 96

GENERAL DESCRIPTION

The ADV7182 automatically detects and converts standard

analog baseband video signals compatible with worldwide NTSC,

PAL, and SECAM standards into a 4:2:2 component video data

stream. This video data stream is compatible with the 8-bit ITU-R

BT.656 interface standard.

External HS, VS, and FIELD signals can provide timing references

for LCD controllers and other video ASICs. The accurate 10-bit

analog-to-digital conversion provides professional quality video

performance for consumer applications with true 8-bit data

resolution. The analog video inputs accept both single-ended,

pseudo-differential, and fully differential composite video signals

as well as S-Video and YPbPr video signals, supporting a wide

range of consumer and automotive video sources.

The ADV7182 along with an external resistor divider provide a

common-mode input range of 4 V, enabling the removal of large

signal, common-mode transients present on the video lines.

Common-mode rejection (CMR) values of up to 80 dB can be

achieved without the need for external amplifier circuitry

The AGC and clamp restore circuitry allow an input video signal

peak-to-peak range to 1.0 V at the analog video input pin of the

ADV7182. Alternatively, these can be bypassed for manual settings.

The ADV7182 can be protected from short-to-battery (STB)

events with standard ac coupling capacitors.

The ADV7182 is programmed via a two-wire, serial bidirectional

port (I2C® compatible) and is fabricated in a 1.8 V CMOS process.

Its monolithic CMOS construction ensures greater functionality

with lower power dissipation. The LFCSP package options make

the decoder ideal for space-constrained portable applications.

The ADV7182 is a versatile one-chip multiformat video decoder

that automatically detects PAL, NTSC, and SECAM standards in

the form of composite, S-Video, and component video. The

ADV7182 can receive composite signals in either single-ended

or differential modes. This makes the ADV7182 ideal for

automotive applications.

The ADV7182 converts these analog video formats into a

digital 8-bit ITU-R BT.656 video stream.

The digital video output stream of the ADV7182 interfaces

easily to a wide range of MPEG encoders, codecs, mobile video

processors, and Analog Devices, Inc., digital video encoders, such

as the ADV7391. External HS, VS, and FIELD signals provide

timing references for LCD controllers and other video ASICs.

OVERVIEW OF THE ANALOG FRONT END

The ADV7182 analog front end (AFE) comprises a single high

speed, 10-bit ADC that digitizes the analog video signal before

applying it to the standard definition processor. The AFE employs

differential channels to the ADC to ensure high performance in

mixed-signal applications and to enable differential CVBS to be

connected directly to the ADV7182

The front end also includes a 3-channel input mux that enables

multiple composite video signals to be applied to the ADV7182.

Current clamps are positioned in front of the ADC to ensure

that the video signal remains within the range of the converter.

A resistor divider network is required before each analog input

channel to ensure that the input signal is kept within the range

of the ADC (see Figure 23). The choice of this resistor divider

ratio provides a common-mode range of up to 4 V. Fine clamping

of the video signal is performed downstream by digital fine

clamping within the ADV7182.

Table 1 shows the three ADC clocking rates that are determined

by the video input format to be processed. These clock rates ensure

4× oversampling per channel for CVBS, Y/C, and YPrPb modes.

The ADV7182 has a fully differential AFE. This allows for inherent

small and large signal noise rejection, improved electromagnetic

interference (EMI), and the ability to absorb ground bounce.

Support is offered for both true differential and pseudo-

differential signals.

Table 1. ADC Clock Rates

Input Format

ADC Clock Rate (MHz)1

Oversampling

Rate per Channel

CVBS

57.27

4×

Y/C (S-Video)2

114

4×

YPrPb2

172

4×

Based on a 28.63636 MHz clock input to the ADV7182.

See INSEL[4:0] in Table 95 for writes needed to set Y/C (S-Video) and YPrPb

modes.

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