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51795B Datasheet(PDF) 82 Page - Microchip Technology |
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51795B Datasheet(HTML) 82 Page - Microchip Technology |
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82 / 100 page ![]() PICkit™ 3 User’s Guide DS51795B-page 82 2010 Microchip Technology Inc. Expressions Combinations of constants and/or symbols separated by arithmetic or logical operators. Extended Microcontroller Mode In extended microcontroller mode, on-chip program memory as well as external mem- ory is available. Execution automatically switches to external if the program memory address is greater than the internal memory space of the PIC18 device. Extended Mode In Extended mode, the compiler will utilize the extended instructions (i.e., ADDFSR, ADDULNK, CALLW, MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK) and the indexed with literal offset addressing. External Label A label that has external linkage. External Linkage A function or variable has external linkage if it can be referenced from outside the module in which it is defined. External Symbol A symbol for an identifier which has external linkage. This may be a reference or a definition. External Symbol Resolution A process performed by the linker in which external symbol definitions from all input modules are collected in an attempt to resolve all external symbol references. Any external symbol references which do not have a corresponding definition cause a linker error to be reported. External Input Line An external input signal logic probe line (TRIGIN) for setting an event based upon external signals. External RAM Off-chip Read/Write memory. Fatal Error An error that will halt compilation immediately. No further messages will be produced. File Registers On-chip data memory, including General Purpose Registers (GPRs) and Special Function Registers (SFRs). Filter Determine by selection what data is included/excluded in a trace display or data file. Flash A type of EEPROM where data is written or erased in blocks instead of bytes. FNOP Forced No Operation. A forced NOP cycle is the second cycle of a two-cycle instruction. Since the PIC microcontroller architecture is pipelined, it prefetches the next instruction in the physical address space while it is executing the current instruction. However, if the current instruction changes the program counter, this prefetched instruction is explicitly ignored, causing a forced NOP cycle. |
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