Revision: 2.85

Specification Update

September 2012

26

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Failure to exit L0s, resulting in a timeout and recovery, can cause a reduction in

performance. In rare cases, the large number of replays may cause a PCIe Hang. Failure

to exit L1 results in a Surprise Down error which may be a fatal error in operating

systems that fully support Advanced Error Reporting.

Workaround: Fix implemented in revised EEPROM version number v1.5 by setting PCIe Init

Configuration 3 word - Bits 4 & 5.

Status:

Fixed.

▼ Return to Summary

21. PCIe: Missing Replay Due to Recovery During TLP Transmission

Problem:

If the replay timer expires during the transmission of a TLP and the LTSSM moves from

L0 to Recovery during the transmission of the same TLP, the expected replay does not

occur. Additionally, the replay timer is disabled, so no further replays will occur unless a

NAK is received.

Implication: This situation should not occur during normal operation. If it does occur while the

upstream switch is waiting for a replay, the result would be a Surprise Down error which

might halt the system.

Workaround: Not needed.

Status:

A1, A2 NoFix

▼ Return to Summary

22. PCIe: LTSSM Moves from L0 to Recovery Only When Receiving TS1/TS2 on All Lanes

Problem:

According to the PCIe specification, the LTSSM should move from L0 to Recovery if a TS1

LTSSM only moves from L0 to Recovery if a TS1 or TS2 ordered set is received on all

configured lanes.

Implication: This situation should not occur during normal operation since the upstream switch will

transmit the TS1 or TS2 ordered sets on all lanes at the same time. If it does occur due to

a broken lane, the result would be a Surprise Down error which might halt the system.

Workaround: None; not necessary since problem does not occur under normal conditions.

23. This entry moved from the Errata to Specification Clarification section (above).

The move makes the issue’s presentation consistent with the positioning in other

products.

24. PCIe: Missing Completion on D3 to D0 Transition

Problem:

When both ports are in D3 and software transitions one port to D0 using a PMCSR write

access which arrives at a specific time relative to exiting L1: completion for the PMCSR

write is correctly provided, but the following transaction does not get a completion.

This bug only occurs when the IOV Enabled EEPROM bit is 1.

Implication: This situation has been observed when using certain operating systems that do not

support IOV during a small fraction of S1 to S0 transitions. If the problem does occur, it

will likely result in a system hang.

Workaround: Do a

ny of the following: