Revision: 2.85

September 2012

Specification Update

27

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If IOV is not required, clear the IOV Enabled bit in the EEPROM (word 0x25, bit 0).

•

Do not use S1. Use S3 instead.

•

Make a BIOS modification to avoid the problematic event timing by providing 30 us

of quiet before and after a PMCSR write access that transfers the port from D3 to

D0. This could be done by adding an ACPI _PS0 method that includes STALLs

surrounding a STORE to PMCSR. Contact Intel for more information.

Status:

A1, A2 NoFix

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25. PCIe: Completion Timeout Settings Not Loaded from EEPROM to GCR

Problem:

The following GCR fields should be loaded from EEPROM word 0x15 but are not:

•

Completion_Timeout_Resend

•

Completion_Timeout_Value (capability version 1 only)

•

Completion_Timeout_Disable (capability version 1 only)

Implication: EEPROM settings are ignored. Hardware default values are used.

Workaround: Software should set the values in the GCR if non-default values are required. This can be

done by the BIOS or the driver.

Status:

A1, A2 NoFix

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26. MSI-X: Descriptor Write-back Not Triggered by EITR Expiration in MSI-X Mode

Problem:

When using MSI-X mode with multiple interrupt vectors, in many cases the descriptor

write-back is not triggered by the expiration of the EITR to which the queue is mapped.

This applies to both Tx and Rx queues.

Implication: Receive queues: If RXDCTL.WTHRESH is greater than 1, large latencies may be seen on

received packets since no descriptor write-back occurs until WTHRESH is reached.

Transmit queues using descriptor write back: If TXDCTL.WTHRESH is greater than 1,

buffers are not released by the driver until WTHRESH is reached.

Transmit queues using Head Write Back: The WB on EITR bit is ineffective and only

descriptors with RS set cause a head write-back.

Workaround: One of the following:

•

The default value of WTHRESH should be used in TXDCTL and RXDCTL. If using

Head Write Back, set the RS bit in all descriptors that should trigger a head write

back.

•

Program all 32 entries of the IVAR array to point to valid interrupt vectors that have

a non-zero EITR value programmed.

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Don't use MSI-X or use only a single vector, and clear GPIE.Multiple_MSIX.

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Use the SWFLUSH bit of TXDCTL and RXDCTL to periodically flush the descriptors

based on an external timer.

Status:

A1, A2 NoFix

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