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82576EB Datasheet(PDF) 34 Page - Intel Corporation

Part # 82576EB
Description  Intel짰 82576EB Gigabit Ethernet Controller Specification Update
PDF  34 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82576EB Datasheet(HTML) 34 Page - Intel Corporation

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Software Clarifications - Intel® 82576EB GbE Controller
Intel® 82576EB GbE Controller
Revision: 2.85
Specification Update
September 2012
34
1.5.5
Software Clarifications
Applies to Intel drivers.
1. While In TCP Segmentation Offload, Each Buffer is Limited to 64 KB
Clarification: The 82576 supports 256 KB TCP packets; however, each buffer is limited to 64 KB since
the data length field in the transmit descriptor is only 16 bits. This restriction increases
driver implementation complexity if the operating system passes down a scatter/gather
element greater than 64KB in length. This can be avoided by limiting the offload size to
64 KB.
Investigation has concluded that the increase in data transfer size does not provide any
noticeable improvements in LAN performance. As a result, Intel network software drivers
limit the data transfer size in all drivers to 64 KB.
Please note that Linux operating systems only support 64 KB data transfers.
For further details about how Intel network software drivers address this issue, refer to
Technical Advisory TA-191.
▼ Return to Summary
2.
Serial Interfaces Programmed By Bit Banging
Clarification: When bit-banging on a serial interface (such as SPI, I2C, or MDIO), it is often necessary
to perform consecutive register writes with a minimum delay between them. However,
simply inserting a software delay between the writes can be unreliable due to hardware
delays on the CPU and PCIe interfaces. The delay at the final hardware interface might be
less than intended if the first write is delayed by hardware more than the second write.
To prevent such problems, a register read should be inserted between the first register
write and the software delay, i.e. “write”, “read”, “software delay”, “write”.
▼ Return to Summary
3.
PF/VF Drivers Should Configure Registers That Are Not Reset By VFLR
Clarification: The following registers are not reset by VFLR and need to be configured by PF or VF in
case of a change to a new configuration (such as VF OS transition):
RDH/T, TDH/T, PSRTYPE, SRRCTL, RXDCTL, TXDCTL, TDWBAL/H, RXCTRL, TXCTRL
▼ Return to Summary
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