DP83848JSQ datasheet(58/80 Pages) TI

58 / 80 page

www.national.com

7.2.9 CD Test and BIST Extensions Register

(CDCTRL1)

Table 29. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B

Bit

Bit Name

Default

Description

15:8

BIST_ERROR_CO

UNT

0, RO

BIST ERROR Counter:

Counts number of errored data nibbles during Packet BIST. This

value will reset when Packet BIST is restarted. The counter sticks

when it reaches its max count.

7:6

RESERVED

0, RW

RESERVED:

Must be zero.

BIST_CONT_MOD

0, RW

Packet BIST Continuous Mode:

Allows continuous pseudo random data transmission without any

break in transmission. This can be used for transmit VOD testing.

This is used in conjunction with the BIST controls in the PHYCR

abled, bit 0 of the 10BTSCR (0x1Ah), JABBER_DIS = 1.

CDPATTEN_10

0, RW

CD Pattern Enable for 10Mb:

1 = Enabled.

0 = Disabled.

RESERVED

0, RW

RESERVED:

Must be zero.

10MEG_PATT_GA

0, RW

Defines gap between data or NLP test sequences:

1 = 15

µs.

0 = 10

µs.

1:0

CDPATTSEL[1:0]

00, RW

CD Pattern Select[1:0]:

If CDPATTEN_10 = 1:

00 = Data, EOP0 sequence

01 = Data, EOP1 sequence

10 = NLPs

11 = Constant Manchester 1s (10MHz sine wave) for harmonic dis-

tortion testing.

DP83848JSQ Datasheet(PDF) 58 Page - Texas Instruments

DP83848JSQ Datasheet(HTML) 58 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL