DP83848JSQ datasheet(23/80 Pages) TI

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3.3.3 Serial Management Preamble Suppression

The DP83848J supports a Preamble Suppression mode

as indicated by a one in bit 6 of the Basic Mode Status

entity (i.e. MAC or other management controller) deter-

mines that all PHYs in the system support Preamble Sup-

pression by returning a one in this bit, then the station

management entity need not generate preamble for each

management transaction.

The DP83848J requires a single initialization sequence of

32 bits of preamble following hardware/software reset.

This requirement is generally met by the mandatory pull-

up resistor on MDIO in conjunction with a continuous

MDC, or the management access made to determine

whether Preamble Suppression is supported.

While the DP83848J requires an initial preamble

sequence of 32 bits for management initialization, it does

not require a full 32-bit sequence between each subse-

quent transaction. A minimum of one idle bit between

management transactions is required as specified in the

IEEE 802.3u specification.

Figure 4. Typical MDC/MDIO Read Operation

Figure 5. Typical MDC/MDIO Write Operation

MDC

MDIO

00 0

11 0 0 00 0 0 0

(STA)

Idle

Start

Opcode

(Read)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

MDIO

(PHY)

0 0 0 1 1 0 00 1 0 0 0 000 0 0 Z

Idle

MDC

MDIO

000

11 0 0 00 0 0 0

(STA)

Idle

Start Opcode

(Write)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

0 0 0

0 00

00 0 0 0 000 Z

Idle

10 0

DP83848JSQ Datasheet(PDF) 23 Page - Texas Instruments

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