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DP83848JSQ Datasheet(PDF) 13 Page - Texas Instruments |
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DP83848JSQ Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 80 page  www.national.com 12 AN0 (LED_LINK) AN1 (LED_SPEED) S, O, PU S, O, PU 22 21 These input pins control the advertised operating mode of the de- vice according to the following table. The value on these pins are set by connecting them to GND (0) or VCC (1) through 2.2 kΩ re- sistors. These pins should NEVER be connected directly to GND or VCC. The value set at this input is latched into the DP83848J at Hard- ware-Reset. The float/pull-down status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. The default for DP83848J is 11 since these pins have an internal pull-up. MII_MODE (RX_DV) S, O, PD 32 MII MODE SELECT: This strapping option determines the oper- ating mode of the MAC Data Interface. Default operation (No pul- lup) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in RMII mode of oper- ation. Since the pin includes an internal pull-down, the default val- ue is 0. The following table details the configuration: LED_CFG (CRS/CRS_DV) S, O, PU 33 LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled via the strap option. All modes are con- figurable via register access. SeeTable 3 for LED Mode Selection. MDIX_EN (RX_ER) S, O, PU 34 MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pull-down will disable Auto- MDIX mode. Signal Name Type Pin # Description AN1 AN0 Advertised Mode 0 0 10BASE-T, Half/Full-Duplex 0 1 100BASE-TX, Half/Full-Duplex 1 0 10BASE-T, Half-Duplex 100BASE-TX, Half-Duplex 1 1 10BASE-T, Half/Full-Duplex 100BASE-TX,Half/Full-Duplex MII_MODE MAC Interface Mode 0MII Mode 1 RMII Mode |
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