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DP83848JSQ Datasheet(PDF) 65 Page - Texas Instruments |
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DP83848JSQ Datasheet(HTML) 65 Page - Texas Instruments |
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65 / 80 page  www.national.com 64 8.2.5 100 Mb/s MII Receive Timing Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. 8.2.6 100BASE-TX Transmit Packet Latency Timing Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode. Parameter Description Notes Min Typ Max Units T2.5.1 RX_CLK High/Low Time 100 Mb/s Normal mode 16 20 24 ns T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode 10 30 ns RX_CLK RXD[3:0] RX_DV T2.5.2 T2.5.1 T2.5.1 Valid Data RX_ER Parameter Description Notes Min Typ Max Units T2.6.1 TX_CLK to PMD Output Pair Latency 100 Mb/s Normal mode 6 bits TX_CLK TX_EN TXD PMD Output Pair (J/K) IDLE DATA T2.6.1 |
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