DP83848JSQ datasheet(10/80 Pages) TI

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1.0 Pin Descriptions

The DP83848J pins are classified into the following inter-

face categories (each interface is described in the sections

that follow):

— Serial Management Interface

— MAC Data Interface

— Clock Interface

— LED Interface

—Reset

— Strap Options

— 10/100 Mb/s PMD Interface

— Special Connect Pins

— Power and Ground pins

Note: Strapping pin option. Please see Section 1.6 for strap

definitions.

All DP83848J signal pins are I/O cells regardless of the

particular use. The definitions below define the functionality

of the I/O cells for each pin.

1.1 SERIAL MANAGEMENT INTERFACE

1.2 MAC DATA INTERFACE

Type: I

Input

Type: O

Output

Type: I/O

Input/Output

Type: PD,PU Internal Pulldown/Pullup

Type: S

Strapping Pin (All strap pins have weak in-

ternal pull-ups or pull-downs. If the default

strap value is needed to be changed then an

external 2.2 k

Ω resistor should be used.

Please see Section 1.6 for details.)

Signal Name

Type

Pin #

Description

MDC

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO

management data input/output serial interface which may be

asynchronous to transmit and receive clocks. The maximum clock

rate is 25 MHz with no minimum clock rate.

MDIO

I/O

MANAGEMENT DATA I/O: Bi-directional management instruc-

tion/data signal that may be sourced by the station management

entity or the PHY. This pin requires a 1.5 k

Ω pullup resistor.

Signal Name

Type

Pin #

Description

TX_CLK

MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100

Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz

reference clock.

Unused in RMII mode. The device uses the X1 reference clock in-

put as the 50 MHz reference for both transmit and receive.

TX_EN

I, PD

MII TRANSMIT ENABLE: Active high input indicates the pres-

ence of valid data inputs on TXD[3:0].

RMII TRANSMIT ENABLE: Active high input indicates the pres-

ence of valid data on TXD[1:0].

TXD_0

TXD_1

TXD_2

TXD_3

I, PD

MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0],

that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s

mode or 25 MHz in 100 Mb/s mode).

RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0],

that accept data synchronous to the 50 MHz reference clock.

RX_CLK

MII RECEIVE CLOCK: Provides the 25 MHz recovered receive

clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.

Unused in RMII mode. The device uses the X1 reference clock in-

put as the 50 MHz reference for both transmit and receive.

RX_DV

O, PD

MII RECEIVE DATA VALID: Asserted high to indicate that valid

data is present on the corresponding RXD[3:0].

RMII Synchronous Receive Data Valid: This signal provides the

RMII Receive Data Valid indication independent of Carrier Sense.

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