DP83848JSQ datasheet(29/80 Pages) TI

29 / 80 page

www.national.com

4.2.2.2 Base Line Wander Compensation

The DP83848J is completely ANSI TP-PMD compliant

and includes Base Line Wander (BLW) compensation.

The BLW compensation block can successfully recover

the TP-PMD defined “killer” pattern.

BLW can generally be defined as the change in the aver-

age DC content, relatively short period over time, of an AC

coupled digital transmission over a given transmission

medium. (i.e., copper wire).

BLW results from the interaction between the low fre-

quency components of a transmitted bit stream and the

frequency response of the AC coupling component(s)

within the transmission system. If the low frequency con-

tent of the digital bit stream goes below the low frequency

pole of the AC coupling transformers then the droop char-

acteristics of the transformers will dominate resulting in

potentially serious BLW.

The digital oscilloscope plot provided in Figure 9 illus-

trates the severity of the BLW event that can theoretically

be generated during 100BASE-TX packet transmission.

This event consists of approximately 800 mV of DC offset

for a period of 120

µs. Left uncompensated, events such

as this can cause packet loss.

4.2.3 Signal Detect

The signal detect function of the DP83848J is incorpo-

rated to meet the specifications mandated by the ANSI

FDDI TP-PMD Standard as well as the IEEE 802.3

100BASE-TX Standard for both voltage thresholds and

timing parameters.

Note that the reception of normal 10BASE-T link pulses

and fast link pulses per IEEE 802.3u Auto-Negotiation by

the 100BASE-TX receiver do not cause the DP83848J to

assert signal detect.

4.2.4 MLT-3 to NRZI Decoder

The DP83848J decodes the MLT-3 information from the

Digital Adaptive Equalizer block to binary NRZI data.

4.2.5 NRZI to NRZ

In a typical application, the NRZI to NRZ decoder is

required in order to present NRZ formatted data to the

descrambler.

4.2.6 Serial to Parallel

The 100BASE-TX receiver includes a Serial to Parallel

converter which supplies 5-bit wide data symbols to the

PCS Rx state machine.

Figure 9. 100BASE-TX BLW Event

DP83848JSQ Datasheet(PDF) 29 Page - Texas Instruments

DP83848JSQ Datasheet(HTML) 29 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL