Electronic Components Datasheet Search
  English  ▼

X  

DAC161S997RGHT Datasheet(PDF) 6 Page - Texas Instruments

Click here to check the latest version.
Part # DAC161S997RGHT
Description  16-bit SPI Programmable DAC for 4-20mA Loops
PDF  27 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC161S997RGHT Datasheet(HTML) 6 Page - Texas Instruments

Back Button DAC161S997RGHT Datasheet HTML 2Page - Texas Instruments DAC161S997RGHT Datasheet HTML 3Page - Texas Instruments DAC161S997RGHT Datasheet HTML 4Page - Texas Instruments DAC161S997RGHT Datasheet HTML 5Page - Texas Instruments DAC161S997RGHT Datasheet HTML 6Page - Texas Instruments DAC161S997RGHT Datasheet HTML 7Page - Texas Instruments DAC161S997RGHT Datasheet HTML 8Page - Texas Instruments DAC161S997RGHT Datasheet HTML 9Page - Texas Instruments DAC161S997RGHT Datasheet HTML 10Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 27 page
background image
DAC161S997
SNAS621 – JUNE 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, these specifications apply for VA = VD = 3.3 V, COMA = COMD = 0 V, TA= 25°C, external bipolar
transistor: 2N3904, RE = 22
Ω, C1 = C2 = C3 = 2.2 nF. Boldface limits are over the temperature range of –40°C ≤ TA ≤
105°C
PARAMETER
TEST CONDITIONS
MIN(1)
TYP
MAX(1)
UNIT
DIGITAL OUTPUT CHARACTERISTICS
VOL
Output Low voltage
Isink = 200 μA
0.4
V
VOH
Output HIGH voltage
Isink = 200 μA
2.6
V
IOZH, IOZL
TRI-STATE leakage current
–10
10
µA
COUT
TRI-STATE output capacitance
5
pF
DIGITAL INTERFACE TIMING
fCLK
SCLK frequency
0
10
MHz
tH
SCLK high time
0.4 / FCLK
50
ns
tL
SCLK low time
0.4 / FCLK
50
ns
tCSB
CSB pulse width
5
40
ns
tCSS
CSB set-up time prior to SCLK rising
5
ns
edge
tSCH
24th rising edge of SCLK to CSB
15
ns
rising edge
tCSH
CSB hold time after the 24th falling
6
10
ns
edge of SCLK
tZSDO
CSB falling edge to SDO valid
10
35
ns
tSDOZ
CSB rising edge to SDO HiZ
10
ns
tDS
SDI data set-up time prior to SCLK
10
ns
rising edge
tDH
SDI data hold time after SCLK rising
6
10
ns
edge
tDO
SDO output data valid
30
ns
SPI Timing Diagrams
Figure 1.
6
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: DAC161S997



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com