DAC161S997

SNAS621 – JUNE 2013

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The acquired data is shifted into an internal 24-bit shift register (MSB first) which is configured as a 24-bit deep

FIFO. As the data is being shifted into the FIFO via the SDI pin, the prior contents of the register are being

shifted out through the SDO output. While CSB is high, SDO is in a high Z-state. At the falling edge of CSB, SDO

presents the MSB of the data present in the shift register. SDO is updated on every subsequent falling edge of

SCLK.

NOTE

The first SDO transition will happen on the first falling edge AFTER the first rising edge of

SCLK when CSB is low.

The 24 bits of data contained in the FIFO are interpreted as an 8-bit COMMAND word followed by 16-bits of

DATA. The general format of the 24-bit data stream is shown in Figure 16. Complete instruction set is tabulated

in the REGISTER SET Section.

Figure 16.

SPI Write

SPI write operation is used to change the state of the device. Handshaking does not occur between the master

and the slave (DAC161S997), and the master must control the communication on the following inputs: SCLK,

CSB, SDI. The format of the data transfer is described in the Serial Interface section.

A write is composed of two sections, 8-bits corresponding to a command and 16-bits of data. A command is

simply the address of the desired register to update. Note that some registers are read-only; a write to these

registers will have no effect on the device operation and the register contents will not change. The user

instruction set is shown in the REGISTER SET section.

During power up or device reset, the register contents of all writable registers are set to the listed values in the

REGISTER SET section.

If the DAC161S997 is used in a highly noisy environment in which SPI errors are potentially an issue, the

DAC161S997 supports a more robust protocol (see OPTIONAL PROTECTED SPI WRITES ).

SPI Read

The read operation requires all 4 wires of the SPI interface, which are SCLK, SCB, SDI, and SDO. The simplest

READ operation occurs automatically during any valid transaction on the SPI bus because the SDO pin of

DAC161S997 always shifts out the contents of the internal FIFO. Therefore the data being shifted in to the FIFO

is verified by initiating another transaction and acquiring data at SDO, allowing only for the verification of FIFO

contents.

The internal registers are accessed by the user through a register read command. A register read command is

formed by setting bit 7 of the command to 1( effectively ORing with 0x80) with the address of the desired register

to be read and sending the resulting 8 bits as the command (see REGISTER SET). For example, the register

read command of the STATUS register (address 0x05) would be 0x85.

A register read requires two SPI transactions to recover the register data. The first transaction shifts in the

register read command; an 8-bits of command byte followed by 16-bits of dummy data. The register read

command transfers the contents of the internal register into the FIFO. The second transaction shifts out the FIFO

contents; an 8-bit command byte (which is a copy of previous transaction) followed by the register data. The

Register Read operation is shown in Figure 17.

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