LOOP+

LOOP-

80k

40

15k

15k

15k

390n

6.8n

220n

1n

15 mV

1 mA

500 mV

DAC161S997

C1

C2

C3

BASE

OUT

COMA

virtual ground

500 nA

DAC161S997

www.ti.com

SNAS621 – JUNE 2013

Figure 14. HART Signal Injection

RC Filter Limitation

In an effort to speed up the transient response of the device the user can reduce the capacitances associated

with the low-pass filter at the output of the

∑Δ modulator. However, to maintain stability margins of the current

Serial Interface

The 4-wire interface is compatible with SPI, QSPI, and MICROWIRE, as well as most DSPs. See the SPI Timing

Diagrams section for timing information about the read and write sequences. The serial interface is comprised of

CSB, SCLK, SDIs and SDO. The DAC161S997 supports both Mode 0 and Mode 3 of the SPI protocol.

A bus transaction is initiated by the falling edge of CSB. When CSB is low, the input data is sampled at the SDI

pin by the rising edge of the SCLK. The output data is asserted on the SDO pin at the falling edge of SCLK.

A valid transfer requires an integer multiple of 24 SCLK cycles. If CSB is raised before the 24th rising edge of the

SCLK, the transfer aborts and a Frame Error is reported. If CSB is held low after the 24th falling edge of the

SCLK and additional SCLK edges occur, the data continues to flow through the FIFO and out the SDO pin.

When CSB transitions high, the internal controller decodes the most recent 24 bits that were received before the

rising edge of CSB. CSB must transition to high after an integer multiple of 24 clock cycles, otherwise a Frame

Error is reported and the transaction is considered invalid. When a valid number of SCLK pulses occur with CSB

low, the DAC then performs the requested operation after CSB transitions high.

Figure 15.

Copyright © 2013, Texas Instruments Incorporated

17

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