GND

dV/dT

VIN

EN/UVLO

ILIM

BFET

OUT

OUT

OUT

VIN

VIN

1

5

6

10

3,

4,

5

VIN

2

EN/

UVLO

+

1.4V

1.35V

4.3V

4.08V

+

UVLO

EN

TSD

220nA

70pF

6V

SWEN

4.8x

80W

10

ILIM

+

VIN

+

ILIMIT

1.6*ILIMIT

10 A

m

6V

GATE

CONTROL

Charge

Pump

Over

Voltage

Thermal

ShutDown

6,

7,

8

28mW

BFET

9

SWEN

22W

2 A

m

SWEN

Current

Sense

1

dV/dT

EP

GND

OUT

Fast Trip

Comp

TPS2592Ax

TPS2592Bx

SLVSC11A – JUNE 2013 – REVISED JUNE 2013

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

DRC PACKAGE

(TOP VIEW)

PIN DESCRIPTIONS

PIN

DESCRIPTION

NAME

NO.

SUPPLY PINS

VIN

3-5

Input Supply Voltage

GND

Power Pad

GND

CONTROL PINS

dV/dT

1

Tie a capacitor from this pin to GND to control the ramp rate of OUT at device turn-on.

EN/UVLO

This is a dual function control pin. When used as an ENABLE pin and pulled down, it shuts off the internal pass

MOSFET and pulls BFET to GND. When pulled high, it enables the device and BFET.

2

As an UVLO pin, it can be used to program different UVLO trip point via external resistor divider.

Connect this pin to the gate of a blocking NFET. See detailed pin description and application note in this

BFET

9

datasheet.

ILIM

10

A resistor from this pin to GND will set the overload and short circuit limit.

LOAD PINS

OUT

6-8

Output of the device

12

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