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LP8543 Datasheet(PDF) 8 Page - Texas Instruments

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Part # LP8543
Description  High-Voltage DC/DC Boost Converter With Integrated FET
PDF  40 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LP8543 Datasheet(HTML) 8 Page - Texas Instruments

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LP8543
SNVS604D – AUGUST 2009 – REVISED MARCH 2013
www.ti.com
Logic Interface Characteristics (continued)
Symbol
Parameter
Condition
Min
Typ
Max
Units
IL
Output Leakage Current
VOUT = 2.8V
-1.0
1.0
µA
Logic Output ALSO
VOL
Output Low Level
IOUT = 3 mA (pull-up current)
0.3
0.5
V
VOH
Output High Level
IOUT = –3 mA (pull-up current)
VLDO - 0.5V VLDO - 0.3V
V
IL
Output Leakage Current
VOUT = 2.8V
-1.0
1.0
µA
I
2C Serial Bus Timing Parameters (SDA, SCLK) (1)
Limit
Symbol
Parameter
Units
Min
Max
fSCLK
Clock Frequency
400
kHz
1
Hold Time (repeated) START Condition
0.6
µs
2
Clock Low Time
1.3
µs
3
Clock High Time
600
ns
4
Setup Time for a Repeated START Condition
600
ns
5
Data Hold Time
50
ns
6
Data Setup Time
100
ns
7
Rise Time of SDA and SCL
20+0.1Cb
300
ns
8
Fall Time of SDA and SCL
15+0.1Cb
300
ns
9
Set-up Time for STOP condition
600
ns
10
Bus Free Time between a STOP and a START
1.3
µs
Condition
Capacitive Load for Each Bus Line
Cb
10
200
ns
Load of 1 pF corresponds to 1 ns.
(1)
ensured by design. VDDIO = 1.65V to 5.5V.
SMBus Timing Parameters (SDA, SCLK)
(1) (2)
Limit
Units
Symbol
Parameter
Min
Max
fSCLK
Clock Frequency
10
100
kHz
1
Hold Time (repeated) START Condition
4.0
µs
2
Clock Low Time
4.7
µs
3
Clock High Time
4.0
50
µs
4
Setup Time for a Repeated START Condition
4.7
µs
5
Data Hold Time
300
ns
6
Data Setup Time
250
ns
7
Rise Time of SDA and SCL
1000
ns
8
Fall Time of SDA and SCL
300
ns
9
Set-up Time for STOP condition
4.0
µs
(1)
ensured by design. VDDIO = 1.65V to 5.5V.
(2)
The switching characteristics of the LP8543 fully meets or exceeds the published System Management Bus (SMBus) Specification
Version 2.0.
8
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Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LP8543



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