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AM3359 Datasheet(PDF) 120 Page - Texas Instruments |
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AM3359 Datasheet(HTML) 120 Page - Texas Instruments |
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120 / 236 page  GMII[x]_MRCLK (Input) 1 2 GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER (Inputs) GMII[x]_TXCLK 2 3 1 4 4 AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 SPRS717F – OCTOBER 2011 – REVISED APRIL 2013 www.ti.com Table 5-10. Timing Requirements for GMII[x]_TXCLK - MII Mode (see Figure 5-7) 10 Mbps 100 Mbps NO. UNIT MIN TYP MAX MIN TYP MAX 1 tc(TX_CLK) Cycle time, TX_CLK 399.96 400.04 39.996 40.004 ns 2 tw(TX_CLKH) Pulse Duration, TX_CLK high 140 260 14 26 ns 3 tw(TX_CLKL) Pulse Duration, TX_CLK low 140 260 14 26 ns 4 tt(TX_CLK) Transition time, TX_CLK 5 5 ns Figure 5-7. GMII[x]_TXCLK Timing - MII Mode Table 5-11. Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode (see Figure 5-8) 10 Mbps 100 Mbps NO. UNIT MIN TYP MAX MIN TYP MAX tsu(RXD-RX_CLK) Setup time, RXD[3:0] valid before RX_CLK 1 tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK 8 8 ns tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK th(RX_CLK-RXD) Hold time RXD[3:0] valid after RX_CLK 2 th(RX_CLK-RX_DV) Hold time RX_DV valid after RX_CLK 8 8 ns th(RX_CLK-RX_ER) Hold time RX_ER valid after RX_CLK Figure 5-8. GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER Timing - MII Mode 120 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 |
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