AM3359 datasheet(148/236 Pages) TI

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DDR_CK

DDR_CKn

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

SPRS717F – OCTOBER 2011 – REVISED APRIL 2013

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5.6.2

mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface

The device has a dedicated interface to mDDR(LPDDR),DDR2, DDR3, and DDR3L SDRAM. It supports

JEDEC standard compliant mDDR(LPDDR), DDR2, DDR3, and DDR3L SDRAM devices with a 16-bit

data path to external SDRAM memory.

For more details on the mDDR(LPDDR), DDR2, DDR3, and DDR3L memory interface, see the EMIF

section of the AM335x Sitara ARM Cortex A-8 Microprocessors (MPUs) Technical Reference Manual

(literature number SPRUH73).

5.6.2.1

mDDR(LPDDR) Routing Guidelines

It is common to find industry references to mobile double data rate (mDDR) when discussing JEDEC

defined low-power double-data rate (LPDDR) memory devices. The following guidelines use LPDDR when

referencing JEDEC defined low-power double-data rate memory devices.

5.6.2.1.1 Board Designs

TI only supports board designs that follow the guidelines outlined in this document. The switching

characteristics and the timing diagram for the LPDDR memory interface are shown in Table 5-31 and

Figure 5-32.

Table 5-31. Switching Characteristics for LPDDR Memory Interface

NO.

PARAMETER

MIN

MAX

UNIT

tc(DDR_CK)

Cycle time, DDR_CK and DDR_CKn

(1)

tc(DDR_CKn)

(1) The JEDEC JESD209B specification only defines the maximum clock period for LPDDR333 and faster speed bin LPDDR memory

devices. To determine the maximum clock period, see the respective LPDDR memory data sheet.

Figure 5-32. LPDDR Memory Interface Clock Timing

5.6.2.1.2 LPDDR Interface

This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing

specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,

and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the

need for a complex timing closure process. For more information regarding the guidelines for using this

LPDDR specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification

application report (literature number SPRAAV0). This application report provides generic guidelines and

approach. All the specifications provided in the data manual take precedence over the generic guidelines

and must be adhered to for a reliable LPDDR interface operation.

5.6.2.1.2.1 LPDDR Interface Schematic

Figure 5-33 shows the schematic connections for 16-bit interface on AM335x device using one x16

LPDDR device. The AM335x LPDDR memory interface only supports 16-bit wide mode of operation. The

AM335x° device can only source one load connected to the DQS[x] and DQ[x] net class signals and one

load connected to the CK and ADDR_CTRL net class signals. For more information related to net classes,

see Section 5.6.2.1.2.8.

148

Peripheral Information and Timings

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