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AM3359 Datasheet(PDF) 213 Page - Texas Instruments |
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AM3359 Datasheet(HTML) 213 Page - Texas Instruments |
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213 / 236 page  AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717F – OCTOBER 2011 – REVISED APRIL 2013 5.11 Multichannel Serial Port Interface (McSPI) For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (literature number SPRUH73). 5.11.1 McSPI Electrical Data and Timing The following timings are applicable to the different configurations of McSPI in master or slave mode for any McSPI and any channel (n). 5.11.1.1 McSPI—Slave Mode Table 5-80. McSPI Timing Conditions—Slave Mode TIMING CONDITION PARAMETER MIN MAX UNIT Input Conditions tr Input signal rise time 5 ns tf Input signal fall time 5 ns Output Condition Cload Output load capacitance 20 pF Table 5-81. Timing Requirements for McSPI Input Timings—Slave Mode (see Figure 5-88) OPP100 OPP50 NO. UNIT MIN MAX MIN MAX 1 tc(SPICLK) Cycle time, SPI_CLK 62.5 124.8 ns 2 tw(SPICLKL) Typical Pulse duration, SPI_CLK low 0.5P(1) 0.5P(1) 0.5P(1) 0.5P(1) ns 3 tw(SPICLKH) Typical Pulse duration, SPI_CLK high 0.5P(1) 0.5P(1) 0.5P(1) 0.5P(1) ns Setup time, SPI_D[x] (SIMO) valid before SPI_CLK 4 tsu(SIMO-SPICLK) 12.92 12.92 ns active edge(2)(3) Hold time, SPI_D[x] (SIMO) valid after SPI_CLK 5 th(SPICLK-SIMO) 12.92 12.92 ns active edge(2)(3) Setup time, SPI_CS valid before SPI_CLK first 8 tsu(CS-SPICLK) 12.92 12.92 ns edge(2) 9 th(SPICLK-CS) Hold time, SPI_CS valid after SPI_CLK last edge(2) 12.92 12.92 ns (1) P = SPI_CLK period. (2) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and capture input data. (3) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. Table 5-82. Switching Characteristics for McSPI Output Timings—Slave Mode (see Figure 5-89) OPP100 OPP50 NO. PARAMETER UNIT MIN MAX MIN MAX Delay time, SPI_CLK active edge to 6 td(SPICLK-SOMI) -4.00 17.12 -4.00 17.12 ns SPI_D[x] (SOMI) transition(1)(2) Delay time, SPI_CS active edge to 7 td(CS-SOMI) 17.12 17.12 ns SPI_D[x] (SOMI) transition(1)(2) (1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and capture input data. (2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 213 Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 |
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