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2. Operational Description

2.2 System Clock Controller

TMP86FS49FG

Figure 2-4 Configuration of Timing Generator

Note 1: In single clock mode, do not set DV7CK to “1”.

Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.

Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care

Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.

Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after

release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.

2.2.2.2 Machine cycle

Instruction execution and peripheral hardware operation are synchronized with the main system clock.

The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different

types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one

machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A

machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.

Timing Generator Control Register

TBTCR

(0036H)

76

5

4

3

2

1

0

(DVOEN)

(DVOCK)

DV7CK

(TBTEN)

(TBTCK)

(Initial value: 0000 0000)

DV7CK

Selection of input to the 7th stage

of the divider

1: fs

R/W

Multi-

plexer

High-frequency

clock fc

Low-frequency

clock fs

Divider

SYSCK

fc/4

fc or fs

Machine cycle counters

Main system clock generator

1

2

1

4

3

2

8

7

10

9

12

11

14

13

16

15

DV7CK

Multiplexer

Timer/

counters

Warm-up

controller

Watchdog

timer

Time base

timer

Divider

output circuit

Serial

interface

A

S

B

Y

S

B0

A0 Y0

B1

A1 Y1

5

6

17 18 19 20 21

TENTATIVE