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2. Operational Description

2.2 System Clock Controller

TMP86FS49FG

Note: After SYSCK is cleared to “0”, executing the instructions is continiued by the low-frequency clock

for the period synchronized with low-frequency and high-frequency clocks.

Note: SLOW mode can also be released by inputting low level on the RESET pin, which immediately performs the reset opera-

tion. After reset, TMP86FS49FG are placed in NORMAL1 mode.

Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms).

SET

(SYSCR2). 7

; SYSCR2<XEN>

LD

(TC3CR), 63H

; Sets mode for TC4, TC3 (16-bit TC, fc for source)

LD

(TC4CR), 05H

LD

(TTREG4), 0F8H

; Sets warm-up time

DI

; IMF

SET

(EIRH). 1

; Enables INTTC4

EI

; IMF

SET

(TC4CR). 3

; Starts TC4, 3

:

PINTTC4:

CLR

(TC4CR). 3

; Stops TC4, 3

CLR

(SYSCR2). 5

; SYSCR2<SYSCK>

(Switches the main system clock to the high-frequency clock)

RETI

:

VINTTC4:

DW

PINTTC4

; INTTC4 vector table

High-frequency clock

Low-frequency clock

Main system clock

SYSCK

TENTATIVE